Alkim Akyurtlu | PERC: Can you shrink RF circuits by 30% by folding them into the third dimension?
00:12:12 - 00:15:01
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Summary of the clip:
Can you shrink RF circuits by 30% by folding them into the third dimension?
This clip presents a compelling case for circuit compaction by moving from planar (2D) to 3D designs using additive manufacturing. The speaker walks through the process of transforming a standard RF power divider into a compact, three-dimensional component built on a pyramid-shaped base. This innovative approach directly addresses the constant demand for smaller, lighter, and more integrated electronic systems, particularly in the aerospace and defense sectors.
A detailed, multi-step hybrid manufacturing process is showcased, demonstrating the integration of multiple technologies. It begins with an SLA-printed polymer base, which is then copper-plated to form the ground plane. Next, a low-loss dielectric layer is precisely printed onto the 3D structure to create the substrate, followed by the aerosol jet printing of the conductive silver traces that form the power divider circuit itself, wrapping around the non-planar surface.
The process highlights the critical steps for achieving vertical integration and connectivity. To connect the 3D component to a standard PCB, dielectric ramps are printed to create a smooth, reliable transition from the board to the pyramid base. Conductive lines are then printed over these ramps, completing the interconnects. The final result is a functional RF component with a 30% footprint reduction compared to its planar equivalent, with measured performance closely matching simulations.
In this short video, you can learn:
* A step-by-step hybrid process for creating 3D RF components.
* How to combine SLA printing, copper plating, and multi-material aerosol jet printing.
* The technique of printing dielectric ramps for reliable 3D interconnects.
š **Clip Abstract** Discover a complete hybrid manufacturing workflow for transforming a planar RF power divider into a 3D component, achieving a 30% footprint reduction. The process combines SLA printing, plating, and multi-material aerosol jet printing to build the circuit on a pyramid structure, including the critical step of printing ramps for vertical interconnects.
š Link in comments š
#3DRFComponents, #HybridAdditiveManufacturing, #AerosolJetPrinting, #3DInterconnects, #AdditiveElectronics, #AerospaceDefense
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00:05:33 - 00:07:23
How can you print tunable RF filters on flexible substrates without high-temperature sintering?
How can you print tunable RF filters on flexible substrates without high-temperature sintering?
The challenge of creating tunable RF components like frequency selective surfaces (FSS) on flexible, low-temperature substrates is significant. Traditional ferroelectric materials like Barium Strontium Titanate (BST) require high-temperature sintering, making them incompatible with common polymers. This clip introduces a novel material solution developed at UMass Lowell to overcome this fundamental limitation, enabling a new class of printed RF devices.
The solution is a nanoparticle-based BST ink that can be processed at low temperatures compatible with flexible substrates. By formulating the ink with BST nanoparticles, the desired electrical properties can be achieved without thermally damaging the underlying polymer. This ink is designed to replace discrete surface-mount varactors, allowing for a fully printed, integrated, and tunable electromagnetic filter directly on the substrate.
The clip details the ink's performance and unique tuning mechanisms. The printed BST ink exhibits a widely adjustable dielectric constant, ranging from 6 to 50, with a low loss tangent in the 10^-3 range, making it ideal for RF applications like antenna miniaturization. It allows for both static tuning (by controlling the ink's dielectric constant during deposition) and dynamic tuning (by applying a bias voltage to the final device), offering versatile control over the filter's frequency response.
In this short video, you can learn:
* The formulation of a low-temperature, nanoparticle-based ferroelectric (BST) ink.
* How this ink enables fully printed, tunable frequency selective surfaces on flexible substrates.
* The key performance metrics, including a tunable dielectric constant (6-50) and low RF loss.
š **Clip Abstract** This clip details the development of a low-temperature, nanoparticle-based BST ink for RF applications. It explains how this material enables fully printed, tunable filters on flexible substrates, offering a wide dielectric constant range and low loss tangent.
š Link in comments š
#TunableRFFilters, #BSTNanoparticleInk, #FlexiblePrintedElectronics, #LowTemperatureProcessing, #RFElectronics, #WearableElectronics
00:15:15 - 00:17:15
How do you eliminate wire bonds and reliably connect bare die to a circuit using only printing?
How do you eliminate wire bonds and reliably connect bare die to a circuit using only printing?
This clip addresses a critical challenge in microelectronics packaging: integrating bare die into a circuit without traditional methods like wire bonding. The speaker presents a complete additive manufacturing workflow for directly connecting a bare die to a PCB. This method offers a path towards higher integration density, improved RF performance by eliminating parasitic inductance from bond wires, and greater mechanical robustness.
The process begins with automated pick-and-place of the bare die onto the circuit board. To manage the sharp vertical transition from the board to the chip surface, a dielectric fillet or ramp is precisely deposited around the chip's edge. This ramp creates a smooth, gradual slope, which is essential for the subsequent printing of reliable conductive traces that bridge the gap between the board's copper pads and the die's contact pads.
A key innovation for ensuring long-term reliability is highlighted: the printing of a dielectric "seam." This small feature acts as a strain relief mechanism, similar to a gooseneck in traditional PCB design, to accommodate the coefficient of thermal expansion (CTE) mismatch between the die, substrate, and inks. This seam prevents the conductive traces from cracking during thermal cycling or solder reflow, dramatically improving the mechanical robustness and lifetime of the interconnect.
In this short video, you can learn:
* A complete additive workflow for integrating bare die without wire bonds.
* The use of printed dielectric ramps to create smooth vertical interconnects.
* A novel technique of printing a dielectric "seam" for strain relief and improved reliability.
š **Clip Abstract** Learn a complete additive process for integrating bare semiconductor die directly onto a circuit board, eliminating the need for wire bonds. This clip details the critical steps, from pick-and-place and printing dielectric ramps to an innovative "seam" printing technique that ensures mechanical robustness against thermal stress.
š Link in comments š
#BareDieIntegration, #PrintedInterconnects, #DielectricRamps, #DielectricStrainRelief, #PrintedElectronics, #FlexibleElectronics