Andree Maindok | Celanese: How do you apply silver sintering paste when complex surface topography makes printing impossible?
00:19:05 - 00:21:23
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Summary of the clip:
How do you apply silver sintering paste when complex surface topography makes printing impossible?
When building complex power electronic modules, stencil or screen printing is highly effective for flat, direct-bonded copper substrates. However, once a chip is already mounted, applying a die-attach material to the top of the chip introduces severe topography challenges that render stencil printing physically impossible.
To resolve this, Celanese engineered a dispensing process capable of depositing silver paste directly onto irregular chip topographies. Through extensive pattern optimization, they compared dotted layouts against meander-style coating patterns to ensure uniform, flat coverage free of voids.
The results demonstrate that an optimized meander dispensing pattern can achieve an excellent shear strength of 51 MPa after sintering. This breakthrough led to the development of specialized formulations like DA 511, featuring tailored rheology specifically optimized for precision dispensing applications.
In this short video, you can learn:
* The processing limitations of stencil and screen printing on non-flat surfaces with complex topography.
* How different dispensing patterns, such as dotted versus meander lines, affect paste flatness and joint coverage.
* The transition from standard stencil-printing pastes to specialized, viscosity-modified dispensing formulations.
š **Clip Abstract** This segment addresses the challenge of applying silver sintering paste to complex chip topographies where screen printing fails. It details how Celanese optimized meander dispensing patterns to achieve a flat, high-strength 51 MPa joint.
#SilverSintering, #DieAttach, #MeanderDispensing, #PrecisionDispensing, #PowerElectronics, #AdvancedPackaging
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00:02:44 - 00:05:18
Why are next-generation power electronics rendering traditional solder joints completely obsolete?
Why are next-generation power electronics rendering traditional solder joints completely obsolete?
As semiconductor technology advances toward higher power densities, wide-bandgap materials like Silicon Carbide (SiC) are rapidly replacing silicon. While SiC devices enable significantly higher operating temperatures and power handling, they expose the limits of conventional solder alloy attachments, which tend to fail under extreme heat and thermal strain.
This transition demands a fundamental redesign of the power electronic packaging stack. In a typical high-power assembly, a direct bonded copper (DBC) substrate is paired with the semiconductor using a silver sintering paste rather than solder to survive the higher operating temperatures.
The primary failure mechanism in these multi-layered structures is the Coefficient of Thermal Expansion (CTE) mismatch between different materials. Sintered silver joints provide the critical mechanical compliance and high thermal conductivity necessary to absorb these cyclic shear stresses without fatiguing over the device's operational lifetime.
In this short video, you can learn:
* Why Silicon Carbide (SiC) chips require a shift from traditional solder alloys to silver sintering.
* The structural stack of direct bonded copper (DBC) substrates and die attach layers.
* How to manage Coefficient of Thermal Expansion (CTE) mismatches during extreme thermal cycling.
š **Clip Abstract** This clip analyzes the transition from silicon to silicon carbide semiconductors and the physical packaging challenges it introduces. It highlights why conventional solders fail under increased power densities and how sintered silver addresses CTE mismatch in multi-layered DBC substrates.
#SilverSintering, #SiliconCarbide, #DirectBondedCopper, #CTEMismatch, #PowerElectronics, #WideBandgap
00:09:51 - 00:11:41
Can avoiding nanoparticles actually create a more reliable and flexible sintered silver joint?
Can avoiding nanoparticles actually create a more reliable and flexible sintered silver joint?
In silver sintering formulations, the relationship between particle size and reactivity is a critical engineering trade-off. While many market alternatives utilize silver nanoparticles to maximize reactivity and lower sintering temperatures, they introduce severe logistics challenges and risk over-sintering the final joint.
Over-sintering leads to an excessively dense silver film that behaves in a brittle, inflexible manner. When exposed to thermal cycling, these ultra-dense connections lack the compliance needed to absorb mechanical stress, causing premature delamination or joint failure.
By utilizing a sub-micron to low-micron particle size distribution under 5 microns, Celanese achieves a controlled sintering process. This maintains an optimal, evenly distributed target porosity of approximately 5 percent (typically 4.6 percent), which provides the mechanical elasticity required to survive harsh thermal shocks.
In this short video, you can learn:
* The critical trade-off between particle size, reactivity, and the risk of over-sintering.
* Why a highly dense sintered silver film can lead to brittle joints and premature mechanical failure.
* The engineering rationale behind targeting an optimal 5 percent porosity for thermal cycling compliance.
š **Clip Abstract** The clip explores why Celanese opts for sub-micron and low-micron silver particles over nanoparticles in their sintering paste formulations. It explains how maintaining a precise 5 percent joint porosity ensures the mechanical flexibility required to survive harsh thermal cycles.
#SilverSintering, #SubMicronSilver, #ControlledPorosity, #ThermalCyclingCompliance, #PowerElectronicsPackaging, #FlexibleElectronics




