Anjana Govil & Matthias Lange | GlobalFoundries: Why add two extra metal layers, then stop at copper instead of aluminium ahead of wafer-to-wafer bonding?
11:48 - 13:14
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Why add two extra metal layers, then stop at copper instead of aluminium ahead of wafer-to-wafer bonding?
The back-end-of-line layer stacks were filtered down to those most interesting for microLED applications. On the left sits an already available offering, stack eight, with a 900 nanometre pitch on its upper two layers. That layer stack provides an optimum between pitch and still allowing a customer to design low IR drop. The decision was then to enhance it rather than replace it.
Adding two additional layers gives customers more flexibility in routing and in power supply routing, and it reduces the IR drop. That optimises the design, and in the end the objective is a homogeneous brightness across the entire large pixel array. The enhancement targets exactly this: flexible routing and a low IR drop so that brightness stays homogeneous over the whole pixel field.
Typically the layers are topped with an aluminium layer. That is standard processing, but it is not suitable for wafer-to-wafer bonding. So processing stops on the last copper layer and the wafer is just passivated. From there the typical processing flow continues, as shown in the middle sequence of the following slide.
In this short video, you can learn:
* Stack eight already provides a 900 nanometre pitch on its upper two layers, an optimum between pitch and letting a customer design low IR drop.
* Two extra layers are added for routing and power supply routing flexibility, reducing IR drop and supporting homogeneous brightness across the entire large pixel array.
* Because an aluminium top layer is not suitable for wafer-to-wafer bonding, processing stops on the last copper layer and the wafer is passivated instead.
📋 **Clip Abstract** Back-end-of-line stack options for microLED applications are compared, with an available stack eight offering 900 nanometre pitch on the upper two layers and a balance between pitch and low IR drop design. The enhancement adds two layers for routing and power supply flexibility, and the flow ends at copper with passivation because aluminium is unsuitable for wafer-to-wafer bonding.
About the speakers:
* Speakers: Anjana Govil, Matthias Lange
* Company: GlobalFoundries
* Event: Eindhoven 2026
* Location: High Tech Campus, Eindhoven
#BEOLStack, #WaferToWaferBonding, #CopperPassivation, #PowerSupplyRouting, #MicroLEDDisplays, #CMOSBackplanes
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Enabling CMOS backplanes for Microdisplays
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03:39 - 04:25
If nearly 50% of people already wear glasses, how big is the smart-glasses market at just 5% adoption?
If nearly 50% of people already wear glasses, how big is the smart-glasses market at just 5% adoption?
Nearly 50% of the world's population wear glasses — a figure described as surprising even to those in the room. If just 5% of those people convert to wearing a smart glass, that alone equals 150 million units. The arithmetic rests on two inputs: the installed base of spectacle wearers and a single-digit attach rate. That modest conversion still yields a volume worth quantifying.
That 150 million-unit figure is framed as significant in its own right. It becomes as significant as watches and tablets and other wearable categories that have been very successful in the recent past. The comparison matters because it places smart glasses alongside product classes that already achieved scale, rather than treating them as a niche experiment. Volume, not novelty, is the benchmark being applied here.
Beyond people who already wear glasses, the opportunity extends to those who do not. New emerging applications, spatial computing among them, are described as able to explore the opportunity ahead for this category. So the addressable base is not limited to the roughly half of the population with spectacles; it widens with use cases that do not require a prescription at all.
In this short video, you can learn:
* Nearly 50% of the world's population wear glasses, setting the initial base for smart glasses.
* A 5% conversion of that base equals 150 million units, comparable to watches, tablets and other successful wearable categories.
* People who do not wear glasses, plus emerging applications such as spatial computing, extend the opportunity further.
📋 **Clip Abstract** Smart glasses are sized from a simple adoption calculation: nearly 50% of the world's population wear glasses, and 5% conversion yields 150 million units. That volume is compared to watches, tablets and other recent wearable successes, while non-spectacle wearers and spatial computing widen the addressable opportunity.
About the speakers:
* Speakers: Anjana Govil, Matthias Lange
* Company: GlobalFoundries
* Event: Eindhoven 2026
* Location: High Tech Campus, Eindhoven
#SmartGlasses, #SpatialComputing, #WearableUnitVolumes, #SpectacleWearers, #AugmentedReality, #HeadMountedDisplays
13:13 - 15:18
Can a customer's GDS layout alone warp a wafer enough to wreck wafer-to-wafer bonding yield?
Can a customer's GDS layout alone warp a wafer enough to wreck wafer-to-wafer bonding yield?
Wafer electrical test conventionally runs as the last step before fab out, leaving imprints on probe pads up to one micrometer high. That height is a killer criterion for the succeeding wafer-to-wafer bonding process. The fix moves wafer electrical test to the second-last layer, then processes the final layer, levelling those imprints. In addition, in-die sort is offered for customers who want yield monitoring on the prime die array.
Wafer warpage is a recurring topic, and it is manageable. Design a high copper density into the thick metal layers, and that copper creates tensile stress that bends the wafer. Warpage stress management in the oxide layers compensates it, and this bow and warpage management can be done in a symmetrical way. So copper loading in thick metals and the oxide stack are the two levers named.
The customer's GDS design has a huge impact on wafer warpage. If a layout uses very long copper lines in only one direction in each subsequent layer, the tensile stress of the copper gains a direction and the wafer bows asymmetrically. That must be considered already during design, and a fab-side solution to address it is also in development.
In this short video, you can learn:
* Probe-pad imprints from wafer electrical test can reach one micrometer and act as a killer criterion for subsequent wafer-to-wafer bonding.
* Moving wafer electrical test to the second-last layer lets the final layer level those imprints, with in-die sort available for prime-die yield monitoring.
* High copper density in thick metal layers creates tensile stress that bends the wafer, and directional long copper lines in the GDS produce asymmetric bow.
📋 **Clip Abstract** Probe-pad imprints up to one micrometer from last-step wafer electrical test threaten wafer-to-wafer bonding, so the test is moved to the second-last layer and the final layer levels the imprints. Warpage from tensile copper stress in thick metal layers is compensated by oxide stress management, yet customer GDS layouts with single-direction long copper lines still bow wafers asymmetrically.
About the speakers:
* Speakers: Anjana Govil, Matthias Lange
* Company: GlobalFoundries
* Event: Eindhoven 2026
* Location: High Tech Campus, Eindhoven
#ProbePadImprint, #WaferToWaferBonding, #CopperTensileStress, #WaferWarpageManagement, #CMOSBackplanes, #Microdisplays
07:30 - 09:13
Why does shrinking microLED pixels from 4 µm to 2 µm push CMOS backplanes down to FinFET?
Why does shrinking microLED pixels from 4 µm to 2 µm push CMOS backplanes down to FinFET?
The LCOS route starts from a 22FX platform run in Dresden, where the final aluminium layers are customised to create a highly reflective surface, the reflectivity the LCOS module needs. That back-end step stays in-house; adding the LCOS and dicing are typically handled by the OSAT. Production starts this year, with volumes expected to ramp significantly next year.
On microLED, the choice of backplane node tracks pixel size. Customers working from four micron to two micron and going further down need 28 nanometre, 22 nanometre and, long term, FinFET. As pixels shrink, the demand for smaller SRAM to enable memory in pixel rises, driven by the higher colour depth being targeted.
Driver voltage is the second lever shaping backplane selection. The platforms have integrated 1.8-volt drivers, a lot of the time stacked, and are also enabling 3.3-volt drivers needed to drive the higher-voltage microLED designs. And a lot of enhancements on back-end-of-line capabilities are being made to make the offering much more relevant to customers in the space.
In this short video, you can learn:
* Customising the final aluminium layers of the 22FX platform in Dresden delivers the reflectivity an LCOS module needs, with production starting this year and volumes ramping next year.
* Pixel sizes from four micron to two micron and below map to 28 nm, 22 nm and long-term FinFET backplanes, because shrinking pixels need smaller SRAM for memory in pixel.
* Backplanes carry integrated 1.8-volt drivers, often stacked, plus 3.3-volt drivers for higher-voltage microLED designs.
📋 **Clip Abstract** LCOS modules built on the 22FX platform add a reflective aluminium back-end before the OSAT attaches the LCOS and dices. For microLED, falling pixel sizes from 4 µm to 2 µm and beyond pull backplane nodes from 28 nm to 22 nm and eventually FinFET, with 1.8 V and 3.3 V drivers plus back-end-of-line work.,,
About the speakers:
* Speakers: Anjana Govil, Matthias Lange
* Company: GlobalFoundries
* Event: Eindhoven 2026
* Location: High Tech Campus, Eindhoven
#LCOS, #22FX, #MicroLEDBackplane, #MemoryInPixel, #MicroDisplay, #CMOSBackplane