Kenneth Lee | NSC - New Silicon Corporation Pte Ltd: What does the internal cross-section of a truly monolithic CMOS-plus-GaN microdisplay look like?

Why does the microLED industry continue to struggle with alignment yields during sub-micron pixel bonding?

The microLED display sector currently sits at a crossroads between aligned bonding and direct monolithic integration. Traditional aligned bonding strategies manufacture the LED arrays and CMOS backplanes separately, attempting to unite them via sub-micron thermal compression or molecular bonding. However, as pixel pitches shrink below 5 microns for high-resolution AR waveguides, mechanical alignment tolerances become a bottleneck, leading to massive yield drops and poor commercial viability.

To avoid alignment limits, direct bonding methods have emerged. For instance, blanket GaN epi-layers can be bonded onto fully completed CMOS wafers, with the microLEDs subsequently fabricated on top of the CMOS. While this solves the spatial alignment bottleneck, it introduces distinct fabrication constraints, requiring custom toolsets and dedicated, non-standard processing lines that can degrade backplane metals and gate dielectrics if thermal budgets are not carefully managed.

New Silicon Corporation (NSC) addresses this process gap by executing a monolithic integration sequence directly inside a standard CMOS foundry backend-of-line (BEOL) flow. Rather than treating the microLED array and silicon backplane as separate entities to be mated, NSC integrates GaN LEDs with un-interconnected silicon transistors on a single wafer. By patterning the LEDs and interconnecting them with multi-level CMOS metallization steps, the entire micro display is fabricated in a single, self-aligned manufacturing flow that achieves high yield and unmatched scalability.

In this short video, you can learn:
* The technical trade-offs between aligned thermal compression/molecular bonding and direct-on-CMOS monolithic bonding.
* How backend-of-line (BEOL) multi-level metallization is leveraged to replace physical chip-to-chip micro-bumping.
* Why standard CMOS manufacturing lines can be repurposed to mass-produce pixelated microLED light engines without custom tools.

📋 **Clip Abstract** Kenneth Lee compares the industry-standard aligned bonding methods with direct bonding techniques for microLED fabrication. He details how NSC's self-aligned, monolithic CMOS-plus-GaN architecture leverages existing semiconductor foundry infrastructure to overcome yield and scaling limitations.

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Can we build high-performance GaN microLEDs underneath active silicon transistors without melting the CMOS?

At the core of NSC's monolithic display technology is a proprietary double-layer transfer process that flips traditional semiconductor assembly on its head. The process begins with a standard Silicon-on-Insulator (SOI) wafer where active silicon transistors and discrete CMOS components are formed but left completely un-interconnected. This partially processed CMOS wafer is temporary-bonded to a silicon handle wafer, and its original thick silicon substrate is entirely removed via selective etching, leaving an ultrathin active device layer.

This ultrathin silicon transistor layer is then permanently bonded to a high-quality 200mm GaN-on-silicon LED epitaxial wafer. At this stage, the combined structure behaves optically and mechanically like a standard silicon wafer, allowing it to easily pass through conventional CMOS fab lines. Windows are photolithographically opened through the active silicon device layer to expose the underlying GaN epitaxial layers, defining where microLED elements, trench isolation structures, and contact vias will be formed.

The critical technical triumph of this process is maintaining a strict low-thermal-budget regime during the subsequent LED definition and metallization. Since the CMOS transistors are already fabricated, all processing steps—including dry etching, contact annealing, and oxide reflow—must remain below the damage threshold of the active silicon devices. Standard chemical mechanical planarization (CMP) and trench refill techniques are used to planarize the surface before a multi-level BEOL metallization interconnects both the underlying LEDs and overlying CMOS driver transistors into a single integrated circuit.

In this short video, you can learn:
* The step-by-step physical chemistry of the double-layer transfer process combining SOI and GaN-on-Silicon epi-wafers.
* How window patterning and selective etching expose underlying GaN layers without degrading surrounding silicon transistors.
* The thermal budget and material compatibility strategies that prevent cross-contamination in standard CMOS fabs.

📋 **Clip Abstract** This clip outlines the step-by-step double-layer transfer and etching sequence used to monolithically fuse CMOS and GaN layers. By using standard CMP, photolithography, and BEOL metal lines, NSC fabricates fully integrated microdisplays on 200mm wafers.

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