Martijn Heck | TU Eindhoven: Silicon photonics offers massive scalability, but can't generate light. So how do we build a complete photonic system-on-chip without a native laser source?
00:08:08 - 00:10:31
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Silicon photonics offers massive scalability, but can't generate light. So how do we build a complete photonic system-on-chip without a native laser source?
The speaker outlines the consolidation of photonic integration platforms into two primary technologies: compound semiconductors (like Indium Phosphide, InP) and CMOS-compatible silicon photonics. While compound semiconductors excel in active components, offering high-performance modulators, detectors, and crucially, integrated lasers, they are built on small, exotic, and costly substrates that are incompatible with mainstream silicon manufacturing. This fundamental incompatibility presents a major barrier to cost-effective, high-volume production.
Conversely, silicon photonics leverages the immense scale, maturity, and cost advantages of the CMOS manufacturing ecosystem. It allows for large-format wafers (300mm) and the creation of excellent low-loss passive components like waveguides. However, silicon's indirect bandgap makes it an extremely inefficient light emitter, meaning it cannot be used to create on-chip lasers. While germanium can be integrated for photodetectors, the lack of a native, efficient light source remains the platform's Achilles' heel.
This dichotomy creates a critical challenge: to meet future demands for bandwidth and energy efficiency, we need the best of both worlds. The ideal photonic integrated circuit (PIC) requires the low-loss passives and manufacturability of silicon, the light-generation capabilities of III-V materials, and tight co-integration with the driving electronics. The central question for the industry, therefore, is not which platform will win, but how to effectively and scalably combine these disparate materials onto a single, silicon-based substrate.
In this short video, you can learn:
* The fundamental trade-offs between compound semiconductor (InP) and silicon photonic platforms.
* Why silicon's indirect bandgap prevents it from being an efficient on-chip light source.
* The three key requirements for future photonic systems: a silicon substrate, integrated III-V materials for lasers, and co-packaged electronics.
๐ **Clip Abstract** Photonic integration is converging on two platforms: high-performance but non-scalable compound semiconductors and highly scalable but laser-less silicon. The key to future high-bandwidth, energy-efficient systems lies in heterogeneously integrating these materials to combine their respective strengths.
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#SiliconPhotonics, #CompoundSemiconductors, #HeterogeneousIntegration, #PhotonicIntegratedCircuits, #AdvancedPackaging, #SystemOnChip
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The road ahead for integrated photonics
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00:11:32 - 00:13:21
How do you achieve sub-micron alignment when bonding a tiny III-V laser die onto a massive silicon photonics wafer?
How do you achieve sub-micron alignment when bonding a tiny III-V laser die onto a massive silicon photonics wafer?
The speaker introduces die bonding as a mature and commercially proven method for integrating III-V materials onto a silicon photonics platform. In this process, a fully processed silicon photonics wafer serves as the target substrate. Small dies of unprocessed III-V material are then bonded directly onto specific locations on this wafer. The critical innovation is that the final, high-precision patterning of the III-V laser structures is performed *after* bonding, using the same advanced lithography tools (like an ASML stepper) employed for the silicon layer.
This post-bonding processing strategy elegantly solves the formidable alignment challenge. Instead of relying on mechanical pick-and-place accuracy, the system leverages the nanometer-scale precision of lithographic alignment. This allows the active III-V waveguide to be perfectly aligned with the underlying silicon waveguide, which is essential for efficient optical coupling. The alignment accuracy required is on the order of 100-200 nanometers, a feat unachievable with traditional die attach methods but standard for modern lithography.
The optical coupling itself is achieved using tapered structures. The light traveling in the silicon waveguide is guided upwards via an adiabatic taper into the III-V material, where it is amplified or lased. A second taper then efficiently couples the light back down into the silicon waveguide for routing elsewhere on the chip. This technique has been successfully commercialized by companies like Intel for high-volume data center transceivers and is now being deployed for next-generation optical compute interconnects, demonstrating its viability for demanding, high-bandwidth applications.
In this short video, you can learn:
* The process flow of heterogeneous die bonding for III-V on silicon integration.
* How post-bonding lithography is used to achieve the required <200nm alignment accuracy for optical coupling.
* The role of adiabatic tapers in efficiently transferring light between the silicon and III-V layers.
๐ **Clip Abstract** Die bonding is a powerful technique for adding laser functionality to silicon photonics by bonding III-V material onto a processed wafer. The key to its success is performing the final III-V device patterning after bonding, using high-precision lithography to achieve the sub-micron alignment necessary for efficient light coupling.
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#HeterogeneousIntegration, #PostBondingLithography, #OpticalWaveguides, #III-VLasers, #OpticalInterconnects, #HighPerformanceComputing
00:16:11 - 00:17:36
What if you could assemble micro-scale photonic components like LEGO bricks, using a high-throughput, massively parallel "pick-and-place" process?
What if you could assemble micro-scale photonic components like LEGO bricks, using a high-throughput, massively parallel "pick-and-place" process?
Micro transfer printing is presented as a novel, versatile assembly technique that bridges the gap between wafer-scale bonding and serial, one-by-one die attachment. The core concept involves fabricating the active components (e.g., III-V lasers) and the passive platform (e.g., a silicon photonics wafer) in their respective, optimized, native fabs. The innovation lies in the preparation of the active components: they are fabricated on a sacrificial layer, creating fully-formed, releasable micro-components, or "coupons," held in place only by fragile tethers.
The assembly is performed using a precisely engineered elastomeric stamp. This stamp can be designed to pick up an array of these coupons from the source wafer in a single, massively parallel operation. When the stamp makes contact and retracts, the kinetic energy is sufficient to break the weak tethers, releasing the coupons from their native substrate. This allows for a high-throughput transfer process, as hundreds or thousands of components can be picked up simultaneously.
The stamp then moves to the target silicon wafer and accurately places the array of coupons onto their designated locations with sub-micron precision (better than 0.5 ยตm), which is critical for photonic applications. This method offers tremendous flexibility, allowing for the sparse placement of expensive III-V material only where it's needed, thus maximizing the use of the source wafer. As a high-throughput, parallel assembly technique, micro transfer printing represents a scalable manufacturing paradigm for creating complex, heterogeneously integrated photonic systems.
In this short video, you can learn:
* The concept of fabricating releasable "coupons" of III-V material on a sacrificial layer.
* How an elastomeric stamp enables massively parallel pick-up and placement of micro-components.
* The benefits of this technique, including high throughput, sub-micron placement accuracy, and efficient use of source materials.
๐ **Clip Abstract** Micro transfer printing is a scalable assembly technology for heterogeneous integration that uses an elastomeric stamp to pick up and place arrays of pre-fabricated micro-scale components. This massively parallel process enables high-throughput, high-precision (sub-micron) assembly of III-V lasers onto silicon photonics wafers, offering a flexible and cost-effective manufacturing solution.
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#MicroTransferPrinting, #HeterogeneousIntegration, #ElastomericStamp, #SiliconPhotonics, #AdvancedPackaging, #AdditiveElectronics