Rajesh Katkar | Adeia: How do angstrom-level CMP, plasma activation and 150–200 °C anneal fuse copper pads into a working conductive bond?
05:55 - 07:29
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How do angstrom-level CMP, plasma activation and 150–200 °C anneal fuse copper pads into a working conductive bond?
Start with a fully processed wafer after back-end-of-line. Deposit a bonding dielectric—oxide, nitride, oxynitride, SiCAn—and embed conductive pads such as copper or nickel on top, then planarize by CMP. The process is packaging but fab-friendly, with stringent requirements: angstrom-scale, sub-nanometer surface roughness on both dielectric and copper. That makes yield sometimes challenging. The dielectric and pads must be coplanar enough for later bonding.
After CMP, activate the surface with plasma activation. Bring the two surfaces together with minimal force at room temperature; a covalent bond forms. As soon as it bonds, starting at room temperature, bond strength improves. Anneal to 50 °C, then 100 °C, and it becomes better and better. At higher annealing temperatures—say 150 °C to 200 °C—copper expands enough to form bonds between opposite copper pads. They fuse together into a working conductive bond interface.
That is the hybrid bond: dielectric bonding plus conductive pad fusion. Compared with the incumbent flip-chip or micro-bump approach, there is really no comparison. Hybrid bonding’s room-temperature covalent contact and anneal-driven copper expansion create a direct conductive interface after CMP and plasma activation. The stringent sub-nanometer roughness requirement applies to both the dielectric and the copper, so yield can be challenging, but the resulting bond interface is both covalent and conductive.
In this short video, you can learn:
* Hybrid bonding deposits a bonding dielectric, embeds copper or nickel pads, and planarizes with CMP to sub-nanometer roughness.
* Plasma activation and minimal-force room-temperature contact form a covalent bond whose strength rises with 50–100 °C annealing.
* At 150–200 °C, copper expands and fuses opposite pads into a working conductive bond interface, unlike flip chip or micro bump.
📋 **Clip Abstract** Hybrid bonding starts with a fully processed wafer and a CMP-planarized bonding dielectric with embedded conductive pads. Plasma activation and room-temperature contact create a covalent bond; 50–200 °C annealing improves strength and expands copper to fuse opposite pads into a conductive interface.
About the speaker:
* Speaker: Rajesh Katkar
* Company: Adeia
* Event: Eindhoven 2026
* Location: High Tech Campus, Eindhoven
#BondingDielectric, #ChemicalMechanicalPolishing, #PlasmaActivation, #CopperPadFusion, #AdvancedPackaging, #HeterogeneousIntegration
This is a highlight of the presentation:
Hybrid Bonding for III-V integration with CMOS
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01:03 - 02:40
Is hybrid bonding a brand-new AI-driven innovation, or does its history stretch back decades into III-V integration?
Is hybrid bonding a brand-new AI-driven innovation, or does its history stretch back decades into III-V integration?
Hybrid bonding looks new because data-center and AI demand created an inflection point three or four years ago, bringing volume, large ASPs and logic-computing interest. But the timeline stretches almost three decades, into the last millennia: Zetronics began direct wafer-to-wafer bonding with an oxide-to-oxide interface, silicon oxide to silicon oxide. One of the first products used III-V integration on aluminum nitride. That early work already established the bonding stack.
Die-to-wafer integration is older still: more than 25 years ago, direct bonding attached a die on its backside to a silicon wafer, with interconnects then formed on the die side. The first die-to-wafer or hybrid bonding prototypes appeared more than 20 years ago using nickel pads. Copper-to-copper came later in wafer-to-wafer format with two-micron pads, about 15 years ago.
So the AI-driven surge did not invent hybrid bonding. The history maps a long R&D evolution: HBM timelines, logic computing, oxide interfaces, III-V on aluminum nitride, nickel pads, then copper pads. The recent inflection is about volume and ASPs entering production, not a new physical principle. Hybrid bonding's lineage runs from direct bonding experiments through die-to-wafer and wafer-to-wafer demonstrations.
In this short video, you can learn:
* Hybrid bonding is almost three decades old, not a recent invention.
* Zetronics used silicon-oxide-to-silicon-oxide wafer-to-wafer direct bonding around 2010, with an early product integrating III-V on aluminum nitride.
* The first die-to-wafer hybrid-bonding prototypes used nickel pads more than 20 years ago, while two-micron copper pads in wafer-to-wafer came about 15 years ago.
📋 **Clip Abstract** This clip traces hybrid bonding from direct wafer-to-wafer and die-to-wafer bonding to nickel-pad prototypes and two-micron copper pads, showing a history almost three decades long. It argues that the recent AI and data-center inflection is a volume and ASP shift in logic computing, not the birth of the technology.
About the speaker:
* Speaker: Rajesh Katkar
* Company: Adeia
* Event: Eindhoven 2026
* Location: High Tech Campus, Eindhoven
#HybridBonding, #WaferToWafer, #DieToWafer, #CopperPads, #AdvancedPackaging, #HeterogeneousIntegration
13:37 - 15:22
What thermal and CTE mismatch challenges arise when integrating III-V micro LEDs with silicon backplanes using hybrid bonding?
What thermal and CTE mismatch challenges arise when integrating III-V micro LEDs with silicon backplanes using hybrid bonding?
III-V integration for micro LED spans display and CPU-style applications. In displays, light moves out; in CPU-style, light goes in. The die footprint differs: displays use five- to ten-micron pitches, while CPU applications may go larger depending on the array—larger die, arrayed larger die, or pixelated larger die. Shortwave infrared sensors use comparatively very large dies, perhaps 25, 30, or 50 millimetre square, for image sensing. Footprint impacts process optimization.
CTE management is the game. Silicon has a CTE of, say, three. The III-V material comes with 50%, 60%, or 100% difference in CTE—a huge impact. In CPU applications, the micro LED emitter sits on top of an optical engine, closer to the ASIC. The ASIC operates at 90C to 100C. This is going to fail if it operates at those temperatures. So it needs optimized for those exposures at very high temperatures.
Cooling may need to be designed, and several other things need to be thought about. The footprint makes a difference—it is huge. Whether the die is for displays, CPU-style light-in applications, or shortwave infrared image sensing, the thermal and CTE mismatches demand careful process optimization. The III-V integration must survive the high-temperature environment near the ASIC. This is the core challenge when integrating III-V micro LEDs with silicon.
In this short video, you can learn:
* Silicon's CTE of about 3 contrasts sharply with III-V materials showing 50%, 60%, or even 100% difference, making CTE management critical.
* Die footprint varies from 5–10 micron pitches for displays to 25–50 millimetre square for shortwave infrared sensors, directly impacting process optimization.
* In CPU applications, the micro LED emitter sits near an ASIC operating at 90–100C, a temperature that will cause failure unless cooling and high-temperature exposure optimization are designed.
📋 **Clip Abstract** III-V integration for micro LEDs spans display, CPU-style light-in, and shortwave infrared image sensing, with die footprints from five-micron pitches to 50-millimetre square sensors. The core challenge is CTE management: silicon's CTE of about three versus III-V materials with 50–100% difference, compounded by ASIC temperatures of 90–100C that demand cooling and careful optimization.
About the speaker:
* Speaker: Rajesh Katkar
* Company: Adeia
* Event: Eindhoven 2026
* Location: High Tech Campus, Eindhoven
#IIIVIntegration, #CTEManagement, #MicroLEDPitch, #ShortwaveInfraredSensors, #MicroLEDDisplays, #HeterogeneousIntegration
07:29 - 08:41
Why is the transition from micro bumps to hybrid bonding considered a massive architectural paradigm shift rather than a simple upgrade?
Why is the transition from micro bumps to hybrid bonding considered a massive architectural paradigm shift rather than a simple upgrade?
Flip chip and micro bump are the incumbent, but the contrast is not incremental. Those interconnects are solder-based, with very large interconnect height, and density in the few hundred interconnects per millimetre square range: 600, 800, 900. Hybrid bonding moves from that to more than a million, and even six million, interconnects. That is a completely different paradigm shift, not a simple upgrade to the existing approach.
The architectural consequence is framed by a travel analogy. If you must go from here to Amsterdam on a two-way-lane freeway, your solutions and problems are one set. Instead of two lanes, you are given 5,000 lanes, 10,000 lanes. The solutions you would come up with, and the kind of cars you would make, are very different. That is the architectural change now appearing in applications from the last three, four years in the logic space and memory space.
So it is a very different approach, although it replaces an incumbent like micro bump. The move from solder-based flip chip and micro bump to hybrid bonding changes the architecture itself. It is not just a density number; it changes the problems, the solutions, and the designs being pursued. The recent logic and memory applications demonstrate this shift. There is really no comparison between the incumbent and hybrid bonding.
In this short video, you can learn:
* Flip chip and micro bump interconnects are solder-based and have very large interconnect height.
* Their density is a few hundred interconnects per millimetre square, cited as 600, 800 or 900.
* Hybrid bonding takes that to more than a million or six million interconnects, forcing different architectures.
📋 **Clip Abstract** The clip contrasts solder-based flip chip and micro bump interconnects with hybrid bonding, moving from a few hundred interconnects per millimetre square to more than a million or six million. It argues this is an architectural paradigm shift, not an upgrade, alongside recent logic and memory applications that show completely different architectures and solutions.
About the speaker:
* Speaker: Rajesh Katkar
* Company: Adeia
* Event: Eindhoven 2026
* Location: High Tech Campus, Eindhoven
#HybridBonding, #MicroBump, #InterconnectDensity, #SolderBasedInterconnect, #HeterogeneousIntegration, #AdvancedPackaging