Solomon Chi | Tera Electronics Corp.: Why does a wide-and-slow MicroLED array with blue emitters and silicon photodiodes make sense for 3.2 Tbps links?
02:19 - 04:07
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Why does a wide-and-slow MicroLED array with blue emitters and silicon photodiodes make sense for 3.2 Tbps links?
The target is 3.2 terabits per second and beyond, aimed at MPO and AOC applications, with a second focus on optical I/O, specifically die-to-die interconnect for heterogeneous packaging. The architecture is described as simple: a standard EOSFP connector, one monolithic IC, image fiber on one side, and another side. The key emitter is the Micro LED array.
Hundreds or even thousands of ICs are used, and the LED array is easy to form. Because the LED is blue, at 420 to 450 nanometre wavelength, silicon material can see it, so a silicon-based photodetector serves as the sensor receiver. That leaves only one additional chip in the build: the Micro LED array itself.
Microsoft last year also proposed a very similar wide-and-slow structure called Mosaic, cited here as the nearest precedent. Earlier the same morning, another speaker presented and shared many new interesting developments around this work. Silicon-based detection at blue wavelengths keeps the receive side simple, and the target stays 3.2 terabits per second and beyond for MPO and AOC.
In this short video, you can learn:
* The link targets 3.2 Tbps and beyond for MPO and AOC, plus die-to-die optical I/O for heterogeneous packaging.
* Blue emission at 420 to 450 nanometres is visible to silicon, so a silicon-based photodetector can act as the sensor receiver.
* Only one additional chip is required: the Micro LED array, with hundreds or even thousands of ICs forming it easily.
📋 **Clip Abstract** A monolithic-IC link built on a standard EOSFP connector and image fiber uses a Micro LED array as emitter and a silicon-based photodetector as receiver, because 420 to 450 nanometre blue light is visible to silicon. The wide-and-slow arrangement targets 3.2 terabits per second and beyond for MPO and AOC and die-to-die interconnect in heterogeneous packaging, mirroring Microsoft's Mosaic proposal.
About the speaker:
* Speaker: Solomon Chi
* Company: Tera Electronics Corp.
* Event: Eindhoven 2026
* Location: High Tech Campus, Eindhoven
#MicroLEDOpticalIO, #SiliconPhotodetector, #WideAndSlowMosaic, #DieToDieInterconnect, #OpticalInterconnect, #HeterogeneousPackaging
This is a highlight of the presentation:
Wide-and-Slow MicroLED Optical I/O for Al Infrastructure
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06:42 - 08:46
Can a MicroLED reach 2 GHz to beat the 200–700 MHz ceiling of display-grade devices?
Can a MicroLED reach 2 GHz to beat the 200–700 MHz ceiling of display-grade devices?
In display-based Micro LED, bandwidth runs about 200 MHz to 500 MHz, with the best rate at 700 MHz, which is not good enough for optical interconnect. The team redesigned the quantum well and redesigned the layer, the EP layer, to speed it up. Their good data is now almost at 2 GHz. That means about 4 Gbit/s per channel, per LED. This addresses the first transceiver requirement: the LED must be very fast.
The second one is an ultra-compact Micro LED array. A traditional LED is a lateral-type PN structure. They use a vertical Micro LED, which is very simple: quantum well, P electrical and electrical transparency, and the pad connects here. Because it is vertical, the footprint is very small and can be very compact—less than 10 micrometers, or even five micrometers. Current spreading is very good, and thermal performance is very good.
In the future, wafer-level integration with silicon CMOS is possible. The vertical Micro LED can be used as a very compact light source array. This follows the first two transceiver requirements: the LED must be very fast, and the array must be ultra-compact. Traditional lateral-type PN structures are replaced by vertical Micro LEDs with quantum wells, P electrical and electrical transparency, and pads connected here.
In this short video, you can learn:
* Display-based Micro LEDs reach only 200–500 MHz, or 700 MHz at best, which is insufficient for optical interconnect.
* Redesigning the quantum well and EP layer raises good data to almost 2 GHz, enabling about 4 Gbit/s per channel per LED.
* Vertical Micro LEDs enable ultra-compact arrays below 10 µm or 5 µm, with good current spreading, thermal performance, and future wafer-level silicon CMOS integration.
📋 **Clip Abstract** The clip explains that display-grade Micro LEDs are limited to roughly 200–700 MHz, so the quantum well and EP layer were redesigned to push good data to almost 2 GHz and about 4 Gbit/s per channel per LED. It then describes a vertical Micro LED for ultra-compact arrays below 10 µm or 5 µm, with good current spreading and thermal performance, and possible future wafer-level integration with silicon CMOS.
About the speaker:
* Speaker: Solomon Chi
* Company: Tera Electronics Corp.
* Event: Eindhoven 2026
* Location: High Tech Campus, Eindhoven
#QuantumWellRedesign, #VerticalMicroLED, #EPLayerEngineering, #WaferLevelCMOSIntegration, #MicroLEDOpticalIO, #OpticalInterconnect
15:30 - 17:24
How does shrinking MicroLED pitch to 25 microns yield 12.8 terabit per second in one millimeter?
How does shrinking MicroLED pitch to 25 microns yield 12.8 terabit per second in one millimeter?
Scaling is the most important advantage of MicroLED. The fiber example has 100,000 cores and a 1.5-millimeter diameter. Current data rate is four giga, and the next step is eight. The setup uses a vertical LED. In one millimeter, the pitch can be 25, so one side has 40 MicroLEDs. That gives 1,600 channels inside a one-millimeter range, which is the scaling result.
With 40 by 40, the result is 1,600 channels in one millimeter. If the data rate reaches eight, then eight times 1,600 gives 12.8 terabit per second in that same one millimeter. The fiber is very thin, below two-millimeter diameter, and flexible. This is how the MicroLED pitch and vertical LED combine in one millimeter.
For the future, 12.8 terabit per second means the transceiver is very small, and the cable will be very small as well. The fiber remains below two millimeters in diameter and flexible. The scaling from 4 to 8 giga and the 25-micron pitch make this channel count possible. The next step is eight, enabling the 12.8-terabit result in one millimeter.
In this short video, you can learn:
* A 100,000-core fiber with a 1.5-millimeter diameter is the example platform.
* A 25-micron pitch allows 40 MicroLEDs per side, giving 40 by 40 and 1,600 channels in one millimeter.
* At an eight data rate, 1,600 channels yield 12.8 terabit per second in one millimeter.
📋 **Clip Abstract** MicroLED scaling is demonstrated with a 100,000-core, 1.5-millimeter fiber and a vertical LED. Using a 25-micron pitch, 40 by 40 gives 1,600 channels in one millimeter, and an eight data rate times 1,600 yields 12.8 terabit per second in a fiber below two millimeters and flexible.
About the speaker:
* Speaker: Solomon Chi
* Company: Tera Electronics Corp.
* Event: Eindhoven 2026
* Location: High Tech Campus, Eindhoven
#100000CoreFiber, #VerticalLED, #25MicronPitch, #12Point8TerabitPerSecond, #OpticalInterconnect, #MicroLED
10:32 - 12:47
Can you build a 12-inch optical I/O without mass transfer or through-hole vias?
Can you build a 12-inch optical I/O without mass transfer or through-hole vias?
The integration route avoids mass transfer and through-hole structures such as TSB or TGV. The starting point is a 12-inch CMOS IC wafer, where each rectangle becomes one monolithic IC. The CMOS IC is bigger because the driver, TI and gearbox circuits consume larger area. In the right corner sits a photodiode array that is embedded during the process. The receiver is therefore already inside the silicon before any LED is added.
Attachment is done chip-on-wafer, a die-to-wafer flow in which the die is the epitaxial chip. Whether the epi wafer is grown at two, four, six or eight inches, it is diced into chips of roughly one by one millimetre. Gold is coated on the chip surface and the chip is flipped onto the CMOS IC. This is metal bonding, nothing special: no exotic alignment or transfer step.
After bonding, three to five mask processes follow. These open the mesa and remove the excess gold layer. Every LED in the array then connects to the CMOS circuitry directly beneath it. That gives a per-pixel electrical path without mass transfer and without through-holes. The flow is compatible with a 12-inch wafer, so the optical I/O array scales with the CMOS line rather than with epitaxial wafer size.
In this short video, you can learn:
* Epitaxial wafers of two, four, six or eight inches are diced into roughly one-by-one-millimetre chips that are gold-coated and flip-bonded to a 12-inch CMOS IC.
* The photodiode array is embedded during the CMOS process and sits in the right corner of each monolithic IC.
* Three to five mask steps open the mesa and strip excess gold, leaving every LED connected to the CMOS directly below it.
📋 **Clip Abstract** This clip describes a chip-on-wafer route to MicroLED optical I/O that avoids mass transfer and through-holes such as TSB or TGV. Epi chips, diced to about one by one millimetre and gold-coated, are flip-bonded onto a 12-inch CMOS IC that already contains the photodiode array, driver, TI and gearbox, then finished with three to five mask steps.
About the speaker:
* Speaker: Solomon Chi
* Company: Tera Electronics Corp.
* Event: Eindhoven 2026
* Location: High Tech Campus, Eindhoven
#MicroLEDOpticalIO, #ChipOnWaferBonding, #CMOSPhotodiodeArray, #MesaEtchMasking, #OpticalInterconnect, #SemiconductorPackaging