Tobias A. Schaedler | HRL Laboratories LLC: How does the melt infiltration process enable the metallization of high aspect ratio curved vias, and what are the key factors influencing its success?
00:08:45 - 00:09:04
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How does the melt infiltration process enable the metallization of high aspect ratio curved vias, and what are the key factors influencing its success?
The speaker introduces a melt infiltration process developed to metallize high aspect ratio curved vias, which cannot be effectively metalized using standard electroplating techniques. This process involves using a copper-indium solder that wets the ceramic material of the printed vias. The wetting property allows capillary action to draw the liquid metal into the vias, effectively filling them.
The success of the melt infiltration process hinges on several key factors. The capillary force, which drives the infiltration, is a function of the surface tension of the solder, the contact angle between the solder and the ceramic, and the radius of the capillary (via). By carefully controlling these parameters, the infiltration process can be optimized to achieve complete filling of the vias.
The speaker mentions that adding titanium to the solder helps to decrease the contact angle, thereby enhancing the wetting and improving the infiltration process. This demonstrates the importance of material selection and process optimization in achieving reliable metallization of high aspect ratio features. The process has demonstrated successful infiltration of vias with aspect ratios up to 150 and diameters as low as 10 micrometers.
In this short video, you can learn:
* The limitations of electroplating for high aspect ratio curved vias.
* The principles of melt infiltration and capillary action.
* The key parameters influencing the success of the melt infiltration process.
š **Clip Abstract** This segment describes a melt infiltration process for metallizing high aspect ratio vias, focusing on the role of capillary action and solder composition. It highlights the ability to fill vias that are not amenable to traditional electroplating methods.
š Link in comments š
#MeltInfiltration, #ViaMetallization, #HighAspectRatioVias, #SolderWetting, #SemiconductorPackaging, #Microelectronics
This is a highlight of the presentation:
Additively manufactured ceramic interposers with curved vias
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00:00:53 - 00:01:10
How does 3D micro-printing compare to traditional packaging technologies in terms of cost and feature size?
How does 3D micro-printing compare to traditional packaging technologies in terms of cost and feature size?
The speaker positions 3D micro-printing as a cost-effective solution for low-volume applications, particularly when compared to traditional packaging technologies. He highlights that 3D micro-printing can compete with PCB technologies, as well as low-temperature and high-temperature co-fired ceramics, especially in scenarios where high volumes are not required. This advantage stems from the ability to save on tooling costs associated with traditional manufacturing methods.
The speaker explicitly states that they are not trying to compete with lithography CMOS for applications requiring the smallest micro-size features. While lithography CMOS excels in achieving extremely small feature sizes, it incurs high costs due to the need for masks and cleanroom environments. Therefore, 3D micro-printing offers a compelling alternative for applications that demand a balance between feature size and cost-effectiveness in low volumes.
The key advantage of 3D micro-printing lies in its ability to bridge the gap between cost and feature size for low-volume applications. By avoiding the high tooling costs of traditional methods and the infrastructure demands of lithography, 3D micro-printing provides a viable solution for specialized packaging needs. This positions it as a valuable technology for prototyping and customized designs in the microelectronics industry.
In this short video, you can learn:
* The cost benefits of 3D micro-printing for low-volume applications.
* How 3D micro-printing compares to PCB, LTCC, and HTCC technologies.
* Why 3D micro-printing is not intended to compete with lithography CMOS.
š **Clip Abstract** This segment compares 3D micro-printing with other packaging technologies, emphasizing its cost-effectiveness for low-volume applications and its niche between PCB/ceramics and lithography CMOS. It highlights the trade-offs between feature size, cost, and volume in selecting the appropriate packaging technology.
š Link in comments š
#3DMicroPrinting, #MicroPackaging, #LTCC, #HTCC, #SemiconductorPackaging, #Microelectronics
00:03:44 - 00:04:08
What are the trade-offs between feature size and print throughput in micro-DLP printing, and how does it impact the feasibility of different applications?
What are the trade-offs between feature size and print throughput in micro-DLP printing, and how does it impact the feasibility of different applications?
The speaker discusses the trade-off between feature size and print throughput in digital light processing (DLP) based micro-printing. While conventional DLP printing offers relatively good print rates with pixel sizes around 40 micrometers, it struggles to produce the smaller via sizes required for advanced packaging applications. Micro-printers that utilize optics to focus the exposure down to two-micrometer pixels can achieve the desired feature sizes, but at a significant cost to print speed.
The print throughput scales approximately with the voxel size cubed. This means that reducing the voxel size by a factor of 10 results in a thousandfold decrease in the print rate. While a two-micrometer pixel size allows for the printing of centimeter-scale parts within a couple of days, further reductions in voxel size, such as those achieved with two-photon lithography, lead to impractically slow print rates, potentially requiring months to print a similar-sized part.
Therefore, the choice of voxel size and printing technology must be carefully considered based on the specific application requirements. For applications where feature size is paramount and throughput is less critical, micro-printers with smaller voxel sizes may be suitable. However, for applications requiring larger parts or higher throughput, a balance must be struck between feature size and print speed.
In this short video, you can learn:
* The relationship between voxel size and print throughput in DLP micro-printing.
* The limitations of using very small voxel sizes for large-scale printing.
* The practical considerations for selecting a printing technology based on application needs.
š **Clip Abstract** This segment explains the inverse relationship between feature size and print speed in micro-DLP printing, highlighting the trade-offs between resolution and throughput. It emphasizes the need to balance these factors based on the specific requirements of the packaging application.
š Link in comments š
#MicroDLPPrinting, #VoxelSize, #PrintThroughput, #FeatureSize, #AdvancedPackaging, #SemiconductorManufacturing