Weichung Ooi | Contrel: Why does traditional aligned bonding limit MicroLED microdisplay yields at commercial scale?
03:15 - 05:05
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Why does traditional aligned bonding limit MicroLED microdisplay yields at commercial scale?
Microdisplay fabrication generally relies on two primary approaches to bring GaN light-emitting elements into the silicon world: aligned bonding and direct bonding. Aligned bonding, practiced by several industry pioneers, requires forming the LEDs and the silicon backplanes separately before bonding them with precise sub-micron alignment. However, this mechanical alignment step introduces significant defect rates, severely limiting overall manufacturing yields and preventing cost-effective commercial scaling.
Direct bonding techniques, such as blanket GaN transfer followed by post-bonding LED fabrication, eliminate the alignment challenge during bonding. Yet, standard direct bonding often requires proprietary tools and custom process lines, creating new hurdles in capital expenditure and manufacturing scalability.
To overcome these roadblocks, a novel approach integrates direct bonding seamlessly within a standard CMOS foundry flow. By forming GaN LEDs after wafer bonding and utilizing conventional multi-level metal interconnects, manufacturers can bypass dedicated packaging lines and leverage existing silicon infrastructure for high-yield, high-volume production.
In this short video, you can learn:
* The fundamental yield and alignment limits of traditional thermo-compression and molecular bonding.
* How direct bonding of blanket GaN films avoids sub-micron mechanical alignment issues.
* The manufacturing trade-offs between custom direct bonding process lines and standard CMOS-compatible integration.
š **Clip Abstract** This clip explains the critical differences between aligned and direct bonding for monolithic microdisplays, highlighting why mechanical alignment limits commercial yields. It outlines how integrating GaN processing directly into standard CMOS backplane fabrication solves these scalability challenges.
š Link in comments š
#DirectBonding, #MonolithicIntegration, #GaNOnSilicon, #ThermoCompressionBonding, #MicroLEDMicrodisplays, #ARMicrodisplays
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08:00 - 10:55
How do you fabricate monolithic CMOS-driven GaN MicroLEDs on a single silicon wafer without degrading the transistors?
How do you fabricate monolithic CMOS-driven GaN MicroLEDs on a single silicon wafer without degrading the transistors?
Monolithic integration of gallium nitride (GaN) LEDs onto silicon CMOS backplanes has historically struggled with thermal budget and material compatibility limitations. A breakthrough "double layer transfer" process addresses this by starting with a standard silicon-on-insulator (SOI) wafer. Crucially, the CMOS process is paused after the discrete transistors are formed but before they are interconnected. This partially processed device layer is bonded to a temporary handle wafer, and its original substrate is removed.
The flipped, ultra-thin silicon device layer is then bonded directly onto a high-quality GaN-on-silicon LED epi-wafer. This stack is processed in a standard silicon facility: windows are opened through the silicon layer to access the underlying GaN material, isolation structures are etched, and the wafer is planarized using chemical mechanical planarization (CMP) and trench-refill techniques.
Finally, standard CMOS back-end-of-line (BEOL) multi-level metallization is used to simultaneously wire up both the silicon transistors and the GaN LEDs. The resulting monolithic integrated circuit eliminates the traditional distinction between a backplane and an LED array, packing digital logic, drivers, and light emitters into a single co-designed chip.
In this short video, you can learn:
* The step-by-step process of double-layer transfer using SOI and handle wafers to flip and expose transistor layers.
* How sub-micron contact windows are opened through silicon to access underlying GaN epi-layers.
* Why utilizing standard CMOS back-end-of-line (BEOL) metallization eliminates the need for separate chip-to-chip packaging.
š **Clip Abstract** This clip describes a double-layer transfer process that monolithically integrates GaN LEDs and CMOS transistors on a single wafer using standard silicon processing. It details how paused CMOS device layers are bonded to GaN epi-wafers and interconnected using standard back-end-of-line metallization.
š Link in comments š
#DoubleLayerTransfer, #MonolithicIntegration, #GaNonSilicon, #BEOLMetallization, #MicroLEDDisplays, #ARLightEngines
12:25 - 13:55
Can microdisplay designers simulate and lay out GaN MicroLEDs using standard silicon EDA tools?
Can microdisplay designers simulate and lay out GaN MicroLEDs using standard silicon EDA tools?
Designing complex monolithic microdisplays has historically been a fragmented process, split between separate optical and silicon design environments. By augmenting standard foundry Process Design Kits (PDKs) with modular GaN LED components, designers can now treat light-emitting elements as standard diodes within standard silicon EDA platforms. This enables microdisplay engineers to design, simulate, and verify entire displays inside familiar CAD ecosystems like Cadence and Synopsys.
With specialized LED parameterized cells (Pcells) and dedicated Design Rule Checking (DRC) and Layout Versus Schematic (LVS) rules, engineers can layout pixels, analog drivers, column controllers, and power management circuits on a single chip. This ensures complete circuit functionality and physical manufacturability before sending the design to the silicon foundry.
This unified design flow eliminates the risks of post-packaging failures. Instead of designing a backplane and an LED array separately and hoping they function together after hybrid bonding, designers can simulate the complete monolithic chip as a single cohesive system, drastically reducing time-to-market.
In this short video, you can learn:
* How GaN LEDs are integrated as modular parameterized cells (Pcells) within standard foundry PDKs.
* The role of DRC and LVS checks in maximizing manufacturing yields for monolithic light-emitting ICs.
* How to co-design and simulate pixels, drivers, and digital logic on a single chip before manufacturing.
š **Clip Abstract** This clip demonstrates how a custom modular PDK allows designers to lay out and simulate GaN MicroLEDs and CMOS driver circuitry on a single chip using standard EDA tools. It explains how this unified design flow reduces post-packaging risks and shortens the development cycle for monolithic microdisplays.
š Link in comments š
#GaNMicroLEDs, #MicroLEDPDK, #MonolithicIntegration, #SiliconEDA, #ARMicrodisplays, #MicroLEDDisplays