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ALL PAST & FUTURE EVENTS AS WELL AS MASTERCLASSES WITH A SINGLE ANNUAL PASS

Electronics Packaging Symposium

4-5 November 2021
10am - 5pm

CET

Virtual Event

This is a virtual symposium with live presentations. Binghamton University  State University of New York

This event will be available as on-demand talks only. This was originally organized by the Integrated Electronics Engineering Center (IEEC) of Binghamton University. Topics covered include Future of Semiconductor Technology | Heterogeneous Integration | AI Hardware | Supercomputers | Quantum Computing | On-Package Integration | Panel Level Packaging | Chiplets and Die Block Assembly | 5G Architectures and Packaging| Materials for Neuromorphic Computing | Photonic Packaging | Printed Microwave Packaging | Future of Semiconductors | High Density Fan-Out Packages | Chiplets and SiP | Liquid Metal | 3D Printed Electronics | Printed Electronics | Energy Storage E-Textiles | Interconnects and Die Attach Technologies | Scaling in interconnects | E-Textiles | Wearable Sensors

Leading global speakers include:
GE Research
ASE
NC State University
NC State University
University at Buffalo
Fraunhofer IZM
IBM Research
HP Labs
Intel
GE Research
Fraunhofer IZM
Tampere University of Technology
Raytheon Missiles and Defense Systems
Prismark Partners
NSWC Crane Division
NSWC Crane Division
Rochester Institute of Technology
Binghamton University
Lockheed Martin
Defense Advanced Research Projects Agency (DARPA)
Auburn
IBM
University of Minnesota
Corning Incorporated
Griffis AF Base
SUNY Polytechnic Institute
Binghamton University
Łukasiewicz - ITR
ASE
US Army Research Laboratory
IBM
Georgia Institute of Technology
Binghamton University
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4 November 2021

Binghamton University

Thursday

Opening Remarks

More Details

10:00am

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Talk Demo

Bahgat Sammakla

Vice President for Research

All, Semiconductor Packaging

Opening Remarks

10:00am

Watch Demo Video
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4 November 2021

GE Research

Thursday

Opening Remarks

More Details

10:10am

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Talk Demo

James LeBlanc

Executive Technology Director

All, Semiconductor Packaging

Opening Remarks

10:10am

Watch Demo Video
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4 November 2021

IBM Research

Thursday

Opening Remarks

More Details

10:10am

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Mukesh V. Khare

Vice President

Semiconductor advances have powered nearly every aspect of technology for over 50 years and continue to push the limits of computing performance. This talk will discuss the most recent advances and what’s next in semiconductor technology. IBM Research has maintained leadership in logic technology, and recently announced a breakthrough that will push scaling to the 2nm node and beyond. The trend will continue, with more innovations in microelectronics increasing functionality, advances in packaging and heterogeneous integration, AI hardware, supercomputers (HPC), and quantum computing. Mukesh will share some of the advances in AI cores for both digital and analog compute, which are expected to deliver huge improvements in performance and efficiency without sacrificing accuracy. The talk will also include a journey through IBM’s Quantum ecosystem, including both the hardware and the community which supports its rapid development The combination of quantum computing and semiconductor technology advances for HPC will be the creation of unseen compute power, dramatically accelerating the rate of scientific discovery, with a profound impact on science and industry.

Bio: Dr. Mukesh V. Khare is Vice President at IBM Research, driving IBM’s Hybrid Cloud research agenda. His team of more than 1000 researchers worldwide is re-defining the future of computing for the next generation workloads such as AI, Machine Learning, High-Performance Computing and their delivery through Hybrid Cloud. Dr. Khare’s areas of responsibilities at IBM range from fundamental materials and device research for semiconductors, novel chip architecture and design, cloud and enterprise systems and software for hybrid cloud.

Throughout his career, Dr. Khare helped build and drive collaborative research alliances with leading companies to create what is next in computing. He championed the formation of the AI Hardware Center in 2019 to drive innovations in AI hardware technologies through public-private partnership. Dr. Khare is also the executive sponsor of IBM’s recently launched Cloud Innovation Lab that helps clients and ecosystem partners advance state-of-the-art in cloud technologies. Over the last decade he established IBM Research site at Albany, NY as the world-wide hub for collaborative research in semiconductor technology and built a platform for advanced logic and packaging technology innovation.

Dr. Khare is a recipient of IBM Corporate Award for his technical accomplishments and is also an IBM Distinguished Engineer. He serves on the Board of Directors for the Semiconductor Research Corporation (SRC) and is an active board member of several research-focused entities. Dr. Khare served as the General Chair of the 2018 Symposia on VLSI Technology, has co-authored more than 100 research papers and holds many U.S. and international patents.

Dr. Khare began his career at IBM in 1998 after finishing his M.S, M. Phil. and Ph.D. degrees from Yale University. He is a strong advocate of diversity and inclusion in the workplace through sponsoring initiatives such as PowerUp for women engineers. A proud father of two and the husband of an architect, Dr. Khare lives in Niskayuna, New York.

All, Semiconductor Packaging

Opening Remarks

10:10am

Semiconductor advances have powered nearly every aspect of technology for over 50 years and continue to push the limits of computing performance. This talk will discuss the most recent advances and what’s next in semiconductor technology. IBM Research has maintained leadership in logic technology, and recently announced a breakthrough that will push scaling to the 2nm node and beyond. The trend will continue, with more innovations in microelectronics increasing functionality, advances in packaging and heterogeneous integration, AI hardware, supercomputers (HPC), and quantum computing. Mukesh will share some of the advances in AI cores for both digital and analog compute, which are expected to deliver huge improvements in performance and efficiency without sacrificing accuracy. The talk will also include a journey through IBM’s Quantum ecosystem, including both the hardware and the community which supports its rapid development The combination of quantum computing and semiconductor technology advances for HPC will be the creation of unseen compute power, dramatically accelerating the rate of scientific discovery, with a profound impact on science and industry.

Bio: Dr. Mukesh V. Khare is Vice President at IBM Research, driving IBM’s Hybrid Cloud research agenda. His team of more than 1000 researchers worldwide is re-defining the future of computing for the next generation workloads such as AI, Machine Learning, High-Performance Computing and their delivery through Hybrid Cloud. Dr. Khare’s areas of responsibilities at IBM range from fundamental materials and device research for semiconductors, novel chip architecture and design, cloud and enterprise systems and software for hybrid cloud.

Throughout his career, Dr. Khare helped build and drive collaborative research alliances with leading companies to create what is next in computing. He championed the formation of the AI Hardware Center in 2019 to drive innovations in AI hardware technologies through public-private partnership. Dr. Khare is also the executive sponsor of IBM’s recently launched Cloud Innovation Lab that helps clients and ecosystem partners advance state-of-the-art in cloud technologies. Over the last decade he established IBM Research site at Albany, NY as the world-wide hub for collaborative research in semiconductor technology and built a platform for advanced logic and packaging technology innovation.

Dr. Khare is a recipient of IBM Corporate Award for his technical accomplishments and is also an IBM Distinguished Engineer. He serves on the Board of Directors for the Semiconductor Research Corporation (SRC) and is an active board member of several research-focused entities. Dr. Khare served as the General Chair of the 2018 Symposia on VLSI Technology, has co-authored more than 100 research papers and holds many U.S. and international patents.

Dr. Khare began his career at IBM in 1998 after finishing his M.S, M. Phil. and Ph.D. degrees from Yale University. He is a strong advocate of diversity and inclusion in the workplace through sponsoring initiatives such as PowerUp for women engineers. A proud father of two and the husband of an architect, Dr. Khare lives in Niskayuna, New York.

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4 November 2021

IBM Research

Thursday

What's Next in Computing

More Details

10:30am

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Mukesh V. Khare

Vice President

Semiconductor advances have powered nearly every aspect of technology for over 50 years and continue to push the limits of computing performance. This talk will discuss the most recent advances and what’s next in semiconductor technology. IBM Research has maintained leadership in logic technology, and recently announced a breakthrough that will push scaling to the 2nm node and beyond. The trend will continue, with more innovations in microelectronics increasing functionality, advances in packaging and heterogeneous integration, AI hardware, supercomputers (HPC), and quantum computing. Mukesh will share some of the advances in AI cores for both digital and analog compute, which are expected to deliver huge improvements in performance and efficiency without sacrificing accuracy. The talk will also include a journey through IBM’s Quantum ecosystem, including both the hardware and the community which supports its rapid development The combination of quantum computing and semiconductor technology advances for HPC will be the creation of unseen compute power, dramatically accelerating the rate of scientific discovery, with a profound impact on science and industry.

Bio: Dr. Mukesh V. Khare is Vice President at IBM Research, driving IBM’s Hybrid Cloud research agenda. His team of more than 1000 researchers worldwide is re-defining the future of computing for the next generation workloads such as AI, Machine Learning, High-Performance Computing and their delivery through Hybrid Cloud. Dr. Khare’s areas of responsibilities at IBM range from fundamental materials and device research for semiconductors, novel chip architecture and design, cloud and enterprise systems and software for hybrid cloud.

Throughout his career, Dr. Khare helped build and drive collaborative research alliances with leading companies to create what is next in computing. He championed the formation of the AI Hardware Center in 2019 to drive innovations in AI hardware technologies through public-private partnership. Dr. Khare is also the executive sponsor of IBM’s recently launched Cloud Innovation Lab that helps clients and ecosystem partners advance state-of-the-art in cloud technologies. Over the last decade he established IBM Research site at Albany, NY as the world-wide hub for collaborative research in semiconductor technology and built a platform for advanced logic and packaging technology innovation.

Dr. Khare is a recipient of IBM Corporate Award for his technical accomplishments and is also an IBM Distinguished Engineer. He serves on the Board of Directors for the Semiconductor Research Corporation (SRC) and is an active board member of several research-focused entities. Dr. Khare served as the General Chair of the 2018 Symposia on VLSI Technology, has co-authored more than 100 research papers and holds many U.S. and international patents.

Dr. Khare began his career at IBM in 1998 after finishing his M.S, M. Phil. and Ph.D. degrees from Yale University. He is a strong advocate of diversity and inclusion in the workplace through sponsoring initiatives such as PowerUp for women engineers. A proud father of two and the husband of an architect, Dr. Khare lives in Niskayuna, New York.

All, Semiconductor Packaging

What's Next in Computing

10:30am

Semiconductor advances have powered nearly every aspect of technology for over 50 years and continue to push the limits of computing performance. This talk will discuss the most recent advances and what’s next in semiconductor technology. IBM Research has maintained leadership in logic technology, and recently announced a breakthrough that will push scaling to the 2nm node and beyond. The trend will continue, with more innovations in microelectronics increasing functionality, advances in packaging and heterogeneous integration, AI hardware, supercomputers (HPC), and quantum computing. Mukesh will share some of the advances in AI cores for both digital and analog compute, which are expected to deliver huge improvements in performance and efficiency without sacrificing accuracy. The talk will also include a journey through IBM’s Quantum ecosystem, including both the hardware and the community which supports its rapid development The combination of quantum computing and semiconductor technology advances for HPC will be the creation of unseen compute power, dramatically accelerating the rate of scientific discovery, with a profound impact on science and industry.

Bio: Dr. Mukesh V. Khare is Vice President at IBM Research, driving IBM’s Hybrid Cloud research agenda. His team of more than 1000 researchers worldwide is re-defining the future of computing for the next generation workloads such as AI, Machine Learning, High-Performance Computing and their delivery through Hybrid Cloud. Dr. Khare’s areas of responsibilities at IBM range from fundamental materials and device research for semiconductors, novel chip architecture and design, cloud and enterprise systems and software for hybrid cloud.

Throughout his career, Dr. Khare helped build and drive collaborative research alliances with leading companies to create what is next in computing. He championed the formation of the AI Hardware Center in 2019 to drive innovations in AI hardware technologies through public-private partnership. Dr. Khare is also the executive sponsor of IBM’s recently launched Cloud Innovation Lab that helps clients and ecosystem partners advance state-of-the-art in cloud technologies. Over the last decade he established IBM Research site at Albany, NY as the world-wide hub for collaborative research in semiconductor technology and built a platform for advanced logic and packaging technology innovation.

Dr. Khare is a recipient of IBM Corporate Award for his technical accomplishments and is also an IBM Distinguished Engineer. He serves on the Board of Directors for the Semiconductor Research Corporation (SRC) and is an active board member of several research-focused entities. Dr. Khare served as the General Chair of the 2018 Symposia on VLSI Technology, has co-authored more than 100 research papers and holds many U.S. and international patents.

Dr. Khare began his career at IBM in 1998 after finishing his M.S, M. Phil. and Ph.D. degrees from Yale University. He is a strong advocate of diversity and inclusion in the workplace through sponsoring initiatives such as PowerUp for women engineers. A proud father of two and the husband of an architect, Dr. Khare lives in Niskayuna, New York.

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4 November 2021

Intel

Thursday

Advanced Packaging Architectures: Opportunities and Challenges

More Details

11:10am

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Babak Sabi

Corporate Vice President and General Manager of Assembly/Test Development

Advanced packaging architectures are today widely acknowledged as being increasingly important to drive performance and cost improvements of microelectronics systems. As a result, several innovative packaging architectures have been announced in recent years. On-package integration provides a compact, power efficient platform for Heterogeneous Integration of diverse IP that support faster time to market and cost/yield benefits. In this talk, I will describe current technology envelopes and future scaling directions for representative advanced packaging architectures. Key areas of focus will be: (1) Interconnect scaling, (2) Power efficient high bandwidth signaling including optical interconnects, (3) Hybrid Bonding, (4) Test challenges for chiplets/die block assembly, and (5) Advanced power delivery technologies. The talk will conclude with a call for broad collaboration across industry and academia in multiple areas including technology R&D, design, standardization, and supply chain development.

Bio: Babak Sabi is a Corporate Vice President and the General Manager of Assembly & Test Technology Development (ATTD) at Intel Corporation. Since 2009, he has been responsible for the company’s packaging, assembly process and test technology development.

Babak joined Intel in 1984. Prior to leading ATTD, he led the Corporate Quality Network within Intel’s Technology & Manufacturing Group from 2002 to 2009. He managed a company-wide network of quality and reliability organizations responsible for product reliability, customer satisfaction and quality business practices.

Babak received his Ph.D. in solid state electronics from Ohio State University in 1984. He has authored ten papers on reliability physics and has received five Intel Achievement Awards. He currently holds two patents.

All, Semiconductor Packaging

Advanced Packaging Architectures: Opportunities and Challenges

11:10am

Advanced packaging architectures are today widely acknowledged as being increasingly important to drive performance and cost improvements of microelectronics systems. As a result, several innovative packaging architectures have been announced in recent years. On-package integration provides a compact, power efficient platform for Heterogeneous Integration of diverse IP that support faster time to market and cost/yield benefits. In this talk, I will describe current technology envelopes and future scaling directions for representative advanced packaging architectures. Key areas of focus will be: (1) Interconnect scaling, (2) Power efficient high bandwidth signaling including optical interconnects, (3) Hybrid Bonding, (4) Test challenges for chiplets/die block assembly, and (5) Advanced power delivery technologies. The talk will conclude with a call for broad collaboration across industry and academia in multiple areas including technology R&D, design, standardization, and supply chain development.

Bio: Babak Sabi is a Corporate Vice President and the General Manager of Assembly & Test Technology Development (ATTD) at Intel Corporation. Since 2009, he has been responsible for the company’s packaging, assembly process and test technology development.

Babak joined Intel in 1984. Prior to leading ATTD, he led the Corporate Quality Network within Intel’s Technology & Manufacturing Group from 2002 to 2009. He managed a company-wide network of quality and reliability organizations responsible for product reliability, customer satisfaction and quality business practices.

Babak received his Ph.D. in solid state electronics from Ohio State University in 1984. He has authored ten papers on reliability physics and has received five Intel Achievement Awards. He currently holds two patents.

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4 November 2021

Break

Thursday

Break

More Details

11:50am

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Talk Demo

Break

11:50am

Watch Demo Video
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4 November 2021

ASE

Thursday

The HIR Village for the Heterogeneous Future

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12:00pm

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William Chen

ASE Fellow & Senior Technical Advisor, Life Fellow of IEEE

Bio: Dr William Chen (Bill) holds the position of ASE Fellow & Senior Technical Advisor at ASE Group. Prior to joining the ASE, he was Director at the Institute of Materials Research & Engineering (IMRE) in Singapore, following a distinguished career at IBM Corporation. Bill is a past President of the IEEE Electronics Packaging Society. He is a Life Fellow of IEEE and a Fellow of ASME. He received the ASME InterPACK Achievement Award in 2007. In 2018, he received the IEEE Electronics Packaging Field Award, recognizing his contribution to electronic packaging, from research & development through industrialization.

Bill chairs the Heterogeneous Integration Roadmap initiative, co-sponsored by 3 IEEE Societies (EPS, EDS & Photonics) together with SEMI & ASME Electronics & Photonics Packaging Division.

All, Semiconductor Packaging

The HIR Village for the Heterogeneous Future

12:00pm

Bio: Dr William Chen (Bill) holds the position of ASE Fellow & Senior Technical Advisor at ASE Group. Prior to joining the ASE, he was Director at the Institute of Materials Research & Engineering (IMRE) in Singapore, following a distinguished career at IBM Corporation. Bill is a past President of the IEEE Electronics Packaging Society. He is a Life Fellow of IEEE and a Fellow of ASME. He received the ASME InterPACK Achievement Award in 2007. In 2018, he received the IEEE Electronics Packaging Field Award, recognizing his contribution to electronic packaging, from research & development through industrialization.

Bill chairs the Heterogeneous Integration Roadmap initiative, co-sponsored by 3 IEEE Societies (EPS, EDS & Photonics) together with SEMI & ASME Electronics & Photonics Packaging Division.

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4 November 2021

Raytheon Missiles and Defense Systems

Thursday

Characterization and Development of Printed Multi-material Interconnects and Passive Elements for Microwave Applications

More Details

12:00pm

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Talk Demo

Susan Trulli

Engineering Fellow

Increasing demands on requirements for high power microwave and mm-wave communications systems need volume compaction but also require a high degree of heat transfer to meet system needs. In many cases, this precludes use of emerging commercial embedded die approaches to volume compaction. Also, complex, low volume, and high value added microwave systems often require repair and replace reworkability at the die level. The Raytheon U-Mass/Lowell (UML) Research Institute (RURI) has developed and demonstrated integration of a three dimensional printed near chip scale interposer. This capability enables die embedment that can accommodate die level reworkability and direct cold plate access for the device. Realization of the interposer includes an nFD print of a 3D insulating structure, a planarizing dielectric, a multi-axes conductor print, a printed gasket and a conformal conductor print over multiple materials at multiple heights to make the final interconnect. This structure is embedded within a PCB assembly leading to circuit card assemblies (CCAs) that can then be stacked for volume efficiency. Robustness to multiple surface mount reflow profiles and thermal cycling will be shared. The developed approach can be used and extended to add functionality beyond the basic interconnect. Details of the fabrication and integration of the interposer will be provided.

Bio: Susan Trulli is a Principal Engineering Fellow in the Advanced Microelectronics Solutions department of Raytheon Missiles and Defense Systems. She is a recognized leader in microelectronics in high reliability microwave packaging, with over 40 years of experience in communication and radar products for defense, space and commercial applications. Susan is very active in the International Microelectronics Assembly and Packaging Society (IMAPS) serving seventeen years on the Executive Council in multiple positions including the presidency and chairing numerous IMAPS advanced technology workshops in RF and Microwave Packaging. Susan is the recipient of multiple awards including Raytheon’s highest technical achievement award, the Thomas K. Phillips Award for Excellence in Technology, the IMAPS Sidney J. Stein International Award and the Society for Women Engineers Patent Recognition Award. Susan is focused on gallium nitride (GaN) packaging solutions for high reliability, high power microwave systems and is currently principal investigator for Embedded Die for High Power Microwave Applications through NextFlex. Susan holds patents in the area of microwave module design and materials as well as in the area of printed electronics, thermal design and plasma applicator materials and construction.

All, Semiconductor Packaging

Characterization and Development of Printed Multi-material Interconnects and Passive Elements for Microwave Applications

12:00pm

Increasing demands on requirements for high power microwave and mm-wave communications systems need volume compaction but also require a high degree of heat transfer to meet system needs. In many cases, this precludes use of emerging commercial embedded die approaches to volume compaction. Also, complex, low volume, and high value added microwave systems often require repair and replace reworkability at the die level. The Raytheon U-Mass/Lowell (UML) Research Institute (RURI) has developed and demonstrated integration of a three dimensional printed near chip scale interposer. This capability enables die embedment that can accommodate die level reworkability and direct cold plate access for the device. Realization of the interposer includes an nFD print of a 3D insulating structure, a planarizing dielectric, a multi-axes conductor print, a printed gasket and a conformal conductor print over multiple materials at multiple heights to make the final interconnect. This structure is embedded within a PCB assembly leading to circuit card assemblies (CCAs) that can then be stacked for volume efficiency. Robustness to multiple surface mount reflow profiles and thermal cycling will be shared. The developed approach can be used and extended to add functionality beyond the basic interconnect. Details of the fabrication and integration of the interposer will be provided.

Bio: Susan Trulli is a Principal Engineering Fellow in the Advanced Microelectronics Solutions department of Raytheon Missiles and Defense Systems. She is a recognized leader in microelectronics in high reliability microwave packaging, with over 40 years of experience in communication and radar products for defense, space and commercial applications. Susan is very active in the International Microelectronics Assembly and Packaging Society (IMAPS) serving seventeen years on the Executive Council in multiple positions including the presidency and chairing numerous IMAPS advanced technology workshops in RF and Microwave Packaging. Susan is the recipient of multiple awards including Raytheon’s highest technical achievement award, the Thomas K. Phillips Award for Excellence in Technology, the IMAPS Sidney J. Stein International Award and the Society for Women Engineers Patent Recognition Award. Susan is focused on gallium nitride (GaN) packaging solutions for high reliability, high power microwave systems and is currently principal investigator for Embedded Die for High Power Microwave Applications through NextFlex. Susan holds patents in the area of microwave module design and materials as well as in the area of printed electronics, thermal design and plasma applicator materials and construction.

Watch Demo Video
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4 November 2021

Georgia Institute of Technology

Thursday

Inkjet-/3D-/4D-Printed “Zero-Power” Flexible Wireless Ultrabroadband Modules for IoT, Smart Agriculture and Smart Cities Applications

More Details

12:30pm

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Manos Tentzeris

Ken Byers Professor in flexible electronics

In this talk, inkjet-/3D-printed antennas, interconnects, “smart” encapsulation and packages, RF electronics, microfluidics and sensors fabricated on glass, PET, paper and other flexible substrates are introduced as a system-level solution for ultra-low-cost mass production of Millimeter-Wave Modules for Communication, Energy Harvesting and Sensing applications. Prof. Tentzeris will touch up the state-of-the-art area of fully-integrated printable broadband wireless modules covering characterization of 3D printed materials up to E-band, novel printable “ramp” interconnects and cavities for IC embedding as well as printable structures for self-diagnostic and anti-counterfeiting packages. The presented approach could potentially set the foundation for the truly convergent wireless sensor ad-hoc networks of the future with enhanced cognitive intelligence and "rugged" packaging. Prof. Tentzeris will discuss issues concerning the power sources of "near-perpetual" RF modules, including flexible miniaturized batteries as well as power-scavenging approaches involving thermal, EM, vibration and solar energy forms. The final step of the presentation will involve examples from shape-changing 4D-printed (origami) packages, reflectarrays and mmW wearable (e.g. biomonitoring) antennas and RF modules. Special attention will be paid on the integration of ultrabroadband (Gb/sec) inkjet-printed nanotechnology-based backscattering communication modules as well as miniaturized printable wireless (e.g.CNT) sensors for Internet of Things (IoT), 5G and smart agriculture/biomonitoring applications. It has to be noted that the talk will review and present challenges for inkjet-printed organic active and nonlinear devices as well as future directions in the area of environmentally-friendly ("green") RF electronics and "smart-skin' conformal sensors.

Bio: Professor Tentzeris was born and grew up in Piraeus, Greece. He graduated from Ionidios Model School of Piraeus in 1987 and he received the Diploma degree in Electrical Engineering and Computer Science (Magna Cum Laude) from the National Technical University in Athens, Greece, in 1992 and the M.S. and Ph.D. degrees in Electrical Engineering and Computer Science from the University of Michigan, Ann Arbor in 1993 and 1998.

He is currently a Ken Byers Professor in the area of flexible electronics with the School of ECE, Georgia Tech and he has published more than 600 papers in refereed Journals and Conference Proceedings, 5 books and 25 book chapters. He has served as the Head of the Electromagnetics Technical Interest Group of the School of ECE, Georgia Tech. Also, he has served as the Georgia Electronic Design Center Associate Director for RFID/Sensors research from 2006-2010 and as the GT-Packaging Research Center (NSF-ERC) Associate Director for RF research and the leader of the RF/Wireless Packaging Alliance from 2003-2006. Also, Dr. Tentzeris is the Head of the A.T.H.E.N.A. Research Group (20 students and researchers) and has established academic programs in 3D Printed RF electronics and modules, flexible electronics, origami and morphing electromagnetics, Highly Integrated/Multilayer Packaging for RF and Wireless Applications using ceramic and organic flexible materials, paper-based RFIDs and sensors, inkjet-printed electronics, nanostructures for RF, wireless sensors, power scavenging and wireless power transfer, Microwave MEM's, SOP-integrated (UWB, mutliband, conformal) antennas and Adaptive Numerical Electromagnetics (FDTD, MultiResolution Algorithms). He was the 1999 Technical Program Co-Chair of the 54th ARFTG Conference and he is currently a member of the technical program committees of IEEE-IMS, IEEE-AP and IEEE-ECTC Symposia. He was the TPC Chair for the IMS 2008 Conference and the Co-Chair of the ACES 2009 Symposium. He was the General Co-Chair of the 2019 IEEE APS Symposium in Atlanta and the Chairman for the 2005 IEEE CEM-TD Workshop. He was the Chair of IEEE-CPMT TC16 (RF Subcommittee) and he was the Chair of IEEE MTT/AP Atlanta Sections for 2003. He is a Fellow of IEEE, a member of MTT-15 Committee, an Associate Member of European Microwave Association (EuMA), a Fellow of the Electromagnetics Academy, and a member of Commission D, URSI and of the the Technical Chamber of Greece. He is the Founder and Chair of the newly formed IEEE MTT-S TC-24 (RFID Technologies). He is one of the IEEE C-RFID DIstinguished Lecturers and he has served as one IEEE MTT-Distinguished Microwave Lecturers (DML) from 2010-2012. His hobbies include basketball, swimming, ping-pong and travel.

All, Semiconductor Packaging

Inkjet-/3D-/4D-Printed “Zero-Power” Flexible Wireless Ultrabroadband Modules for IoT, Smart Agriculture and Smart Cities Applications

12:30pm

In this talk, inkjet-/3D-printed antennas, interconnects, “smart” encapsulation and packages, RF electronics, microfluidics and sensors fabricated on glass, PET, paper and other flexible substrates are introduced as a system-level solution for ultra-low-cost mass production of Millimeter-Wave Modules for Communication, Energy Harvesting and Sensing applications. Prof. Tentzeris will touch up the state-of-the-art area of fully-integrated printable broadband wireless modules covering characterization of 3D printed materials up to E-band, novel printable “ramp” interconnects and cavities for IC embedding as well as printable structures for self-diagnostic and anti-counterfeiting packages. The presented approach could potentially set the foundation for the truly convergent wireless sensor ad-hoc networks of the future with enhanced cognitive intelligence and "rugged" packaging. Prof. Tentzeris will discuss issues concerning the power sources of "near-perpetual" RF modules, including flexible miniaturized batteries as well as power-scavenging approaches involving thermal, EM, vibration and solar energy forms. The final step of the presentation will involve examples from shape-changing 4D-printed (origami) packages, reflectarrays and mmW wearable (e.g. biomonitoring) antennas and RF modules. Special attention will be paid on the integration of ultrabroadband (Gb/sec) inkjet-printed nanotechnology-based backscattering communication modules as well as miniaturized printable wireless (e.g.CNT) sensors for Internet of Things (IoT), 5G and smart agriculture/biomonitoring applications. It has to be noted that the talk will review and present challenges for inkjet-printed organic active and nonlinear devices as well as future directions in the area of environmentally-friendly ("green") RF electronics and "smart-skin' conformal sensors.

Bio: Professor Tentzeris was born and grew up in Piraeus, Greece. He graduated from Ionidios Model School of Piraeus in 1987 and he received the Diploma degree in Electrical Engineering and Computer Science (Magna Cum Laude) from the National Technical University in Athens, Greece, in 1992 and the M.S. and Ph.D. degrees in Electrical Engineering and Computer Science from the University of Michigan, Ann Arbor in 1993 and 1998.

He is currently a Ken Byers Professor in the area of flexible electronics with the School of ECE, Georgia Tech and he has published more than 600 papers in refereed Journals and Conference Proceedings, 5 books and 25 book chapters. He has served as the Head of the Electromagnetics Technical Interest Group of the School of ECE, Georgia Tech. Also, he has served as the Georgia Electronic Design Center Associate Director for RFID/Sensors research from 2006-2010 and as the GT-Packaging Research Center (NSF-ERC) Associate Director for RF research and the leader of the RF/Wireless Packaging Alliance from 2003-2006. Also, Dr. Tentzeris is the Head of the A.T.H.E.N.A. Research Group (20 students and researchers) and has established academic programs in 3D Printed RF electronics and modules, flexible electronics, origami and morphing electromagnetics, Highly Integrated/Multilayer Packaging for RF and Wireless Applications using ceramic and organic flexible materials, paper-based RFIDs and sensors, inkjet-printed electronics, nanostructures for RF, wireless sensors, power scavenging and wireless power transfer, Microwave MEM's, SOP-integrated (UWB, mutliband, conformal) antennas and Adaptive Numerical Electromagnetics (FDTD, MultiResolution Algorithms). He was the 1999 Technical Program Co-Chair of the 54th ARFTG Conference and he is currently a member of the technical program committees of IEEE-IMS, IEEE-AP and IEEE-ECTC Symposia. He was the TPC Chair for the IMS 2008 Conference and the Co-Chair of the ACES 2009 Symposium. He was the General Co-Chair of the 2019 IEEE APS Symposium in Atlanta and the Chairman for the 2005 IEEE CEM-TD Workshop. He was the Chair of IEEE-CPMT TC16 (RF Subcommittee) and he was the Chair of IEEE MTT/AP Atlanta Sections for 2003. He is a Fellow of IEEE, a member of MTT-15 Committee, an Associate Member of European Microwave Association (EuMA), a Fellow of the Electromagnetics Academy, and a member of Commission D, URSI and of the the Technical Chamber of Greece. He is the Founder and Chair of the newly formed IEEE MTT-S TC-24 (RFID Technologies). He is one of the IEEE C-RFID DIstinguished Lecturers and he has served as one IEEE MTT-Distinguished Microwave Lecturers (DML) from 2010-2012. His hobbies include basketball, swimming, ping-pong and travel.

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4 November 2021

IBM

Thursday

Heterogeneous Integration for Al Workloads

More Details

12:30pm

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Kamal Slkka

Engineering Manager

Semiconductor scaling to smaller dimensions has led to tremendous improvement in electronic systems performance. Computer systems that used to occupy several rooms are now available in the palm of your hand. However, as semiconductor scaling saturates, other paradigms are necessary for improving the systems performance. One such paradigm of performance improvement is advanced packaging of heterogeneous chips from different semiconductor nodes, different construction and different sources - often called heterogeneous integration (HI). HI is necessary because system performance is required to grow 1000x over the next 7-10 years, especially for Artificial Intelligence (AI) applications. A subset of AI, called machine learning, relies of artificial neural networks that simulate a human brain. In this talk, we compare and contrast the different HI packaging options which include conventional 2D single-chip and multi-chip packages with high-density laminates, package-on-package (PoP) configurations, 2.5D silicon interposers, silicon bridge packages, and fully 3D stacked packages. Many of these configurations are being developed in the IBM AI Hardware Research Center (AIRC). We then elaborate on the Direct Bonded Heterogeneous Integration Si-bridge packaging scheme.

Bio: Kamal Sikka is a Senior Technical Staff Member at IBM. He joined IBM after obtaining his PhD degree in Mechanical Engineering with a focus in Thermal Sciences from Cornell University. His initial work at IBM focused on thermal solution development, e.g., thin-gap thermal paste technology, for IBM OEM customers such as Compaq/HP. This was followed by IBM server thermal solution development such as an Adhesive Thermal Interface coupled to SiC and Diamond heat spreaders.

Kamal then took on the management of the IBM Packaging Development Thermal Development and Modeling department. He transformed the Advanced Thermal Lab with introduction of multiple automated thermal chip-package testers and initiated the Mechanical Analysis Lab as the package substrate technology transitioned from ceramic to organic laminate materials. His team delivered multiple advanced thermal solutions for IBM Systems such as advanced TIMs, diamond heat spreaders, dual heat spreaders and package integrated heat sinks. He was also the leader of the thermal qualification teams for IBM's ASIC menu packages from Cu08, Cu65, Cu45, Cu32, and FX-14 technologies. Besides developing thermal solutions, Kamal led the IBM package modeling and simulation teams, developing modeling protocols for IBM's laminate package technology. Kamal also led task forces for resolving the Microsoft Xbox issues on a consultancy basis, and solder interconnect delamination in workload simulator systems.

Subsequently Kamal served in the senior manager role for the Packaging Development team with Unit Process responsibilities spanning from C4, CPI, laminate, Bond & Assembly and thermal development. Under his leadership, the team reduced the C4 pitch for IBM server packages, co-developed an advanced TIM with an industrial partner, and conducted fundamental research on glass interposers.

Kamal then transitioned from IBM Systems to IBM Research initiating the Heterogeneous Integration (HI) effort and defining the HI strategy. He has led the establishment of the HI Lab at Albany NY. The HI lab integrates material characterization, thermal analysis, mechanical analysis, Bond & Assembly, and reliability equipment in one location. He is also the technical leader for IBM Direct Bonded Heterogeneous Integration (DBHi) Si-bridge and stacked Si-microcooler technologies.

All, Semiconductor Packaging

Heterogeneous Integration for Al Workloads

12:30pm

Semiconductor scaling to smaller dimensions has led to tremendous improvement in electronic systems performance. Computer systems that used to occupy several rooms are now available in the palm of your hand. However, as semiconductor scaling saturates, other paradigms are necessary for improving the systems performance. One such paradigm of performance improvement is advanced packaging of heterogeneous chips from different semiconductor nodes, different construction and different sources - often called heterogeneous integration (HI). HI is necessary because system performance is required to grow 1000x over the next 7-10 years, especially for Artificial Intelligence (AI) applications. A subset of AI, called machine learning, relies of artificial neural networks that simulate a human brain. In this talk, we compare and contrast the different HI packaging options which include conventional 2D single-chip and multi-chip packages with high-density laminates, package-on-package (PoP) configurations, 2.5D silicon interposers, silicon bridge packages, and fully 3D stacked packages. Many of these configurations are being developed in the IBM AI Hardware Research Center (AIRC). We then elaborate on the Direct Bonded Heterogeneous Integration Si-bridge packaging scheme.

Bio: Kamal Sikka is a Senior Technical Staff Member at IBM. He joined IBM after obtaining his PhD degree in Mechanical Engineering with a focus in Thermal Sciences from Cornell University. His initial work at IBM focused on thermal solution development, e.g., thin-gap thermal paste technology, for IBM OEM customers such as Compaq/HP. This was followed by IBM server thermal solution development such as an Adhesive Thermal Interface coupled to SiC and Diamond heat spreaders.

Kamal then took on the management of the IBM Packaging Development Thermal Development and Modeling department. He transformed the Advanced Thermal Lab with introduction of multiple automated thermal chip-package testers and initiated the Mechanical Analysis Lab as the package substrate technology transitioned from ceramic to organic laminate materials. His team delivered multiple advanced thermal solutions for IBM Systems such as advanced TIMs, diamond heat spreaders, dual heat spreaders and package integrated heat sinks. He was also the leader of the thermal qualification teams for IBM's ASIC menu packages from Cu08, Cu65, Cu45, Cu32, and FX-14 technologies. Besides developing thermal solutions, Kamal led the IBM package modeling and simulation teams, developing modeling protocols for IBM's laminate package technology. Kamal also led task forces for resolving the Microsoft Xbox issues on a consultancy basis, and solder interconnect delamination in workload simulator systems.

Subsequently Kamal served in the senior manager role for the Packaging Development team with Unit Process responsibilities spanning from C4, CPI, laminate, Bond & Assembly and thermal development. Under his leadership, the team reduced the C4 pitch for IBM server packages, co-developed an advanced TIM with an industrial partner, and conducted fundamental research on glass interposers.

Kamal then transitioned from IBM Systems to IBM Research initiating the Heterogeneous Integration (HI) effort and defining the HI strategy. He has led the establishment of the HI Lab at Albany NY. The HI lab integrates material characterization, thermal analysis, mechanical analysis, Bond & Assembly, and reliability equipment in one location. He is also the technical leader for IBM Direct Bonded Heterogeneous Integration (DBHi) Si-bridge and stacked Si-microcooler technologies.

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4 November 2021

ASE

Thursday

Semiconductor Package Design Solution for High Density Fan-out Packaging – Chiplets & SiP

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1:00pm

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Alex Wang

Manager

There is great need for multi-die packaging – Chipletes & SiP – to meet the needs of High Performance Computing for Data Ceteers, 5G, Accelerators, AI & ML, & Autonomous Driving applicatiopns and more. A good example of the package type used in such high-performance computing product mass production is Silicon Interposer IC package with ultra-high density I/O, for high performance GPU, and high-speed networking devices, Between the ASIC chip and the HBM stack, a lot of high-speed signal lines and thousands of small vias are connected. In addition the silicon interposer has an important structure-TSV (Through Silicon Via) to act as the connection between the ASIC chips or the HBM chips and the package substrate. Considering productivity and cost, there is great need to develop an advanced packaging solution to fill in the “Gap” between Flip Chip BGA based high density build up substrate and silicon Inteerposer with TSV. One such solution would be high density Fan-Out based upon the well known and well established robust Wafter Level Fanout process and manufacturing infrastructure.

In this paper, we report on an internally developed semiconductor package design flow and platform is proposed for FOCoS package. The platform integrates with semiconductor package design solution and integrated circuit (IC) design solution. It can balance the developing schedule and cost in the design stage of FOCoS. The design flow of FOCoS includes physical design, design rule check (DRC), layout versus schematic (LVS) check and full wave electromagnetic (EM) analysis. In physical design, the major design platform is still based on conventional package design solution like Cadence Allegro APD+ or Mentor XPD. But, to speed up design cycle time, the auto-router for FOCoS RDL design is used in IC design solution. A self-developing program linking to conventional package design solution and IC design solution is applied on the two different file format transferred. Therefore, the FOCoS RDL designer can utility the auto-router to complete the preliminary design, then transfer the design file to conventional package design platform for modification. Once the design is completed, the DRC and LVS can confirm the correctness in rules and interconnection. The difference with IC design flow, it utilizes package netlist to do LVS check in this platform, not schematics. Hence, it easily uses the program of LVS to do 3D IC check. In addition, the location of DRC error can be imported to conventional package design platform and the designer can fast fix the error in conventional package design platform. Finally, the full wave 3D solver extracts the S-parameter of die-to-die or die-to-HBM interconnection for electrical analysis. A real case using the design flow is demonstrated with design cycle time reduction. This design flow is integrated in the package & assembly PDK for HD Fanout package. We shall incorporate AI & ML tools to futher optimize the design process in the future.

Bio: Chen-Chao Wang received the M.S.E.E. degree in electronic engineering from the National Taiwan University of Science and Technology, Taipei, in 1998 and Ph.D. degree in electrical engineering from the National Sun Yat-sen University, Kaohsiung, in 2008, respectively. From 1998 to 2003, he was a Research Engineer at Industrial Technology Research Institute, Hsinchu, Taiwan. In 2006, he joined Advanced Semiconductor Engineering Inc., Kaohsiung, Taiwan, where he is in charge of Division of Product Design. His researching direction includes power integrity and signal integrity analysis in high-speed digital systems and mmWave antenna-in-package design.

All, Semiconductor Packaging

Semiconductor Package Design Solution for High Density Fan-out Packaging – Chiplets & SiP

1:00pm

There is great need for multi-die packaging – Chipletes & SiP – to meet the needs of High Performance Computing for Data Ceteers, 5G, Accelerators, AI & ML, & Autonomous Driving applicatiopns and more. A good example of the package type used in such high-performance computing product mass production is Silicon Interposer IC package with ultra-high density I/O, for high performance GPU, and high-speed networking devices, Between the ASIC chip and the HBM stack, a lot of high-speed signal lines and thousands of small vias are connected. In addition the silicon interposer has an important structure-TSV (Through Silicon Via) to act as the connection between the ASIC chips or the HBM chips and the package substrate. Considering productivity and cost, there is great need to develop an advanced packaging solution to fill in the “Gap” between Flip Chip BGA based high density build up substrate and silicon Inteerposer with TSV. One such solution would be high density Fan-Out based upon the well known and well established robust Wafter Level Fanout process and manufacturing infrastructure.

In this paper, we report on an internally developed semiconductor package design flow and platform is proposed for FOCoS package. The platform integrates with semiconductor package design solution and integrated circuit (IC) design solution. It can balance the developing schedule and cost in the design stage of FOCoS. The design flow of FOCoS includes physical design, design rule check (DRC), layout versus schematic (LVS) check and full wave electromagnetic (EM) analysis. In physical design, the major design platform is still based on conventional package design solution like Cadence Allegro APD+ or Mentor XPD. But, to speed up design cycle time, the auto-router for FOCoS RDL design is used in IC design solution. A self-developing program linking to conventional package design solution and IC design solution is applied on the two different file format transferred. Therefore, the FOCoS RDL designer can utility the auto-router to complete the preliminary design, then transfer the design file to conventional package design platform for modification. Once the design is completed, the DRC and LVS can confirm the correctness in rules and interconnection. The difference with IC design flow, it utilizes package netlist to do LVS check in this platform, not schematics. Hence, it easily uses the program of LVS to do 3D IC check. In addition, the location of DRC error can be imported to conventional package design platform and the designer can fast fix the error in conventional package design platform. Finally, the full wave 3D solver extracts the S-parameter of die-to-die or die-to-HBM interconnection for electrical analysis. A real case using the design flow is demonstrated with design cycle time reduction. This design flow is integrated in the package & assembly PDK for HD Fanout package. We shall incorporate AI & ML tools to futher optimize the design process in the future.

Bio: Chen-Chao Wang received the M.S.E.E. degree in electronic engineering from the National Taiwan University of Science and Technology, Taipei, in 1998 and Ph.D. degree in electrical engineering from the National Sun Yat-sen University, Kaohsiung, in 2008, respectively. From 1998 to 2003, he was a Research Engineer at Industrial Technology Research Institute, Hsinchu, Taiwan. In 2006, he joined Advanced Semiconductor Engineering Inc., Kaohsiung, Taiwan, where he is in charge of Division of Product Design. His researching direction includes power integrity and signal integrity analysis in high-speed digital systems and mmWave antenna-in-package design.

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4 November 2021

NC State University

Thursday

Liquid Metals for Soft and Additive Electronics

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1:30pm

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Michael Dickey

Professor

This talk will discuss efforts to additively pattern and utilize liquid metals as conductive inks for stretchable, soft, and reconfigurable electronics1. Alloys of gallium have metallic conductivity, yet have low viscosity, low toxicity, and negligible volatility. Despite the large surface tension of the metal, it can be patterned into non-spherical 2D and 3D shapes due to the presence of an ultra-thin oxide skin that forms on its surface, as shown in the image.

Liquid metal is extremely soft and flows in response to stress to retain electrical continuity under extreme deformation. By embedding the metal into elastomeric or gel substrates, it is possible to form soft electrodes, stretchable antennas, and ultra-stretchable wires that maintain metallic conductivity up to ~800% strain. The resulting conductors are self-healing. The metals can also be filled into microchannels or hollow fibers for capacitive touch sensors, and mechanically tough fibers. It is also possible to 3D print the metal for source and drain contacts for transistors and as interconnects for energy harvesters. More recently, we demonstrated that liquid metal circuits can also be used for soft, tactile logic2.

Perhaps one of the more unique aspects of liquid metals is the ability to manipulate their shape for reconfigurable electronics. Electrochemistry can deposit and remove the oxide layer to manipulate the interfacial tension—a dominante force at the microscale—over an enormous range. Reductive potentials remove the oxide layer and put the metal in a state of high tension. However, oxidative potentials deposit the oxide layer on the metal and put it in a state of low tension. Experiments suggest the tension could be near zero using less than one volt. Unlike electrowetting, which can require hundreds of volts, here, the changes result due to electrochemically deposited species on the metal surface.

Bio: Michael Dickey received a BS in Chemical Engineering from Georgia Institute of Technology (1999) and a PhD from the University of Texas (2006) under the guidance of Professor Grant Willson. From 2006-2008 he was a post-doctoral fellow in the lab of Professor George Whitesides at Harvard University. He is currently the Camille and Henry Dreyfus Professor in the Department of Chemical & Biomolecular Engineering at NC State University. He completed a sabbatical at Microsoft in 2016. Michael’s research interests include soft matter (liquid metals, gels, polymers) for soft and stretchable devices (electronics, energy harvesters, textiles, and soft robotics).

All, Semiconductor Packaging

Liquid Metals for Soft and Additive Electronics

1:30pm

This talk will discuss efforts to additively pattern and utilize liquid metals as conductive inks for stretchable, soft, and reconfigurable electronics1. Alloys of gallium have metallic conductivity, yet have low viscosity, low toxicity, and negligible volatility. Despite the large surface tension of the metal, it can be patterned into non-spherical 2D and 3D shapes due to the presence of an ultra-thin oxide skin that forms on its surface, as shown in the image.

Liquid metal is extremely soft and flows in response to stress to retain electrical continuity under extreme deformation. By embedding the metal into elastomeric or gel substrates, it is possible to form soft electrodes, stretchable antennas, and ultra-stretchable wires that maintain metallic conductivity up to ~800% strain. The resulting conductors are self-healing. The metals can also be filled into microchannels or hollow fibers for capacitive touch sensors, and mechanically tough fibers. It is also possible to 3D print the metal for source and drain contacts for transistors and as interconnects for energy harvesters. More recently, we demonstrated that liquid metal circuits can also be used for soft, tactile logic2.

Perhaps one of the more unique aspects of liquid metals is the ability to manipulate their shape for reconfigurable electronics. Electrochemistry can deposit and remove the oxide layer to manipulate the interfacial tension—a dominante force at the microscale—over an enormous range. Reductive potentials remove the oxide layer and put the metal in a state of high tension. However, oxidative potentials deposit the oxide layer on the metal and put it in a state of low tension. Experiments suggest the tension could be near zero using less than one volt. Unlike electrowetting, which can require hundreds of volts, here, the changes result due to electrochemically deposited species on the metal surface.

Bio: Michael Dickey received a BS in Chemical Engineering from Georgia Institute of Technology (1999) and a PhD from the University of Texas (2006) under the guidance of Professor Grant Willson. From 2006-2008 he was a post-doctoral fellow in the lab of Professor George Whitesides at Harvard University. He is currently the Camille and Henry Dreyfus Professor in the Department of Chemical & Biomolecular Engineering at NC State University. He completed a sabbatical at Microsoft in 2016. Michael’s research interests include soft matter (liquid metals, gels, polymers) for soft and stretchable devices (electronics, energy harvesters, textiles, and soft robotics).

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4 November 2021

SUNY Polytechnic Institute

Thursday

Materials Development and Integration Strategies for Neuromorphic Computing and AI Hardware

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1:30pm

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Nathaniel Cady

Empire Innovation Professor of Nanobioscience

Neuromorphic and AI computing hardware is trending away from traditional von Neumann computational architectures. This transition is opening the door to a wide range of novel devices and integration solutions. Over the past 10 years, my research group has focused on fabrication and integration strategies for CMOS-compatible, non-volatile, analog memory devices (aka: memristors). These memristive devices have the potential to act as neuronal synapses in neural networks, but can also function as tunable elements in array-based accelerators. Introducing unique materials and novel memristive devices into the traditional CMOS fabrication process presents many challenges, from both the process integration and packaging standpoint. In this presentation I will discuss integration strategies that we have used to develop novel hardware solutions.

Bio: Prof. Cady obtained his BA and Ph.D. from Cornell University in Ithaca, NY. He is currently an Empire Innovation Professor of Nanobioscience in the Colleges of Nanoscale Science & Engineering at SUNY Polytechnic Institute. Prof. Cady has active research interests in the development of novel biosensor technologies and biology-inspired nanoelectronics, including novel hardware for neuromorphic computing.

All, Semiconductor Packaging

Materials Development and Integration Strategies for Neuromorphic Computing and AI Hardware

1:30pm

Neuromorphic and AI computing hardware is trending away from traditional von Neumann computational architectures. This transition is opening the door to a wide range of novel devices and integration solutions. Over the past 10 years, my research group has focused on fabrication and integration strategies for CMOS-compatible, non-volatile, analog memory devices (aka: memristors). These memristive devices have the potential to act as neuronal synapses in neural networks, but can also function as tunable elements in array-based accelerators. Introducing unique materials and novel memristive devices into the traditional CMOS fabrication process presents many challenges, from both the process integration and packaging standpoint. In this presentation I will discuss integration strategies that we have used to develop novel hardware solutions.

Bio: Prof. Cady obtained his BA and Ph.D. from Cornell University in Ithaca, NY. He is currently an Empire Innovation Professor of Nanobioscience in the Colleges of Nanoscale Science & Engineering at SUNY Polytechnic Institute. Prof. Cady has active research interests in the development of novel biosensor technologies and biology-inspired nanoelectronics, including novel hardware for neuromorphic computing.

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4 November 2021

Auburn

Thursday

Superconducting Interconnect Technologies for Cryogenic and Quantum Systems

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2:00pm

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Michael Hamilton

Director of Alabama Micro/Nano Science and Technology Center

Superconducting electronics and quantum systems are experiencing a significant growth in interest due to recent successes in superconducting quantum computing. Cryogenic electronics systems present a unique set of challenges for complex, densely integrated systems with large numbers of components and cables/interconnects often spanning multiple temperature stages. Conventional microwave co-axial cables that are currently in common use can stress volume and thermal constraints of these systems. Suitable connectors for such systems are also needed. In this presentation, I will describe our R&D efforts on high performance, multi-conductor superconducting flexible cables and connectors made using thin-film and wafer-level fabrication approaches. These interconnects have high microwave performance to multiple 10’s of GHz, low mass, and low thermal cross-section structures. This hardware shows great promise as interconnect structures for future superconducting and cryogenic electronics systems, including superconducting microwave quantum computing applications.

Bio: Dr. Michael C. Hamilton obtained a BS in Electrical Engineering from Auburn University in 2000 and MS and PhD in Electrical Engineering from The University of Michigan in 2003 and 2005, respectively. From 2006 to 2010, he was at MIT-Lincoln Laboratory (Lexington, MA), where he worked on a range of microwave and solid-state device projects. Dr. Hamilton joined the Electrical and Computer Engineering Department of Auburn University in 2010 and is now James B. Davis Professor and Director of the Alabama Micro/Nano Science and Technology Center (AMNSTC). He is the Auburn University IEEE Student Chapter Faculty Advisor. Dr. Hamilton is involved with IEEE MTT-S: Education Committee, Chair of MTT-7 Technical Committee on Microwave Superconductivity and Quantum Technologies, producer/moderator of the IEEE MTT-S Webinar Series. He is currently serving on the editorial board of a new open access journal: IEEE Journal of Microwaves. His current interests and areas of research include superconductive electronics and technologies for quantum systems, micro/nano fabrication, packaging and integration of high-speed systems, signal and power integrity of densely integrated systems, application of micro and nanostructures for enhanced performance of RF and microwave systems and packaging for extreme environments (both high and low temperature).

All, Semiconductor Packaging

Superconducting Interconnect Technologies for Cryogenic and Quantum Systems

2:00pm

Superconducting electronics and quantum systems are experiencing a significant growth in interest due to recent successes in superconducting quantum computing. Cryogenic electronics systems present a unique set of challenges for complex, densely integrated systems with large numbers of components and cables/interconnects often spanning multiple temperature stages. Conventional microwave co-axial cables that are currently in common use can stress volume and thermal constraints of these systems. Suitable connectors for such systems are also needed. In this presentation, I will describe our R&D efforts on high performance, multi-conductor superconducting flexible cables and connectors made using thin-film and wafer-level fabrication approaches. These interconnects have high microwave performance to multiple 10’s of GHz, low mass, and low thermal cross-section structures. This hardware shows great promise as interconnect structures for future superconducting and cryogenic electronics systems, including superconducting microwave quantum computing applications.

Bio: Dr. Michael C. Hamilton obtained a BS in Electrical Engineering from Auburn University in 2000 and MS and PhD in Electrical Engineering from The University of Michigan in 2003 and 2005, respectively. From 2006 to 2010, he was at MIT-Lincoln Laboratory (Lexington, MA), where he worked on a range of microwave and solid-state device projects. Dr. Hamilton joined the Electrical and Computer Engineering Department of Auburn University in 2010 and is now James B. Davis Professor and Director of the Alabama Micro/Nano Science and Technology Center (AMNSTC). He is the Auburn University IEEE Student Chapter Faculty Advisor. Dr. Hamilton is involved with IEEE MTT-S: Education Committee, Chair of MTT-7 Technical Committee on Microwave Superconductivity and Quantum Technologies, producer/moderator of the IEEE MTT-S Webinar Series. He is currently serving on the editorial board of a new open access journal: IEEE Journal of Microwaves. His current interests and areas of research include superconductive electronics and technologies for quantum systems, micro/nano fabrication, packaging and integration of high-speed systems, signal and power integrity of densely integrated systems, application of micro and nanostructures for enhanced performance of RF and microwave systems and packaging for extreme environments (both high and low temperature).

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4 November 2021

Rochester Institute of Technology

Thursday

Printed Electronics Via On-Demand Jetting of Liquid Metal Droplets

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2:00pm

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Dennis Cormier

Professor

This presentation will explore the use of on-demand liquid metal droplet jetting to fabricate printed circuit patterns. Through proper control of drop size, jetting frequency, and drop spacing, solid metal traces whose conductivities match that of the bulk metal have been fabricated on temperature sensitive flexible polymer substrates. The process uses inexpensive wire, rather than nanoparticle ink, as the feedstock material. Pre and post-processing steps normally used with nanoparticle ink processes, such as substrate cleaning and ink drying + curing, are eliminated. The presentation will include examples of non-planar printing as well as 3D printed features without the need for support structures.

Bio: Denis Cormier is RIT’s Earl W. Brinkman Professor and Director of the New York State funded AMPrint Center for Advanced Technology. Dr. Cormier has worked in the area of 3D printing and related additive processes for nearly 25 years. Since joining RIT in 2009, his research has focused on technologies such as multi-material inkjet deposition, direct-write processes including aerosol printing and microdispensing, and pulsed photonic curing. Most recently, he has been focused on development of a liquid metal droplet jetting process for highly conductive flexible electronics with excellent substrate adhesion.

All, Semiconductor Packaging

Printed Electronics Via On-Demand Jetting of Liquid Metal Droplets

2:00pm

This presentation will explore the use of on-demand liquid metal droplet jetting to fabricate printed circuit patterns. Through proper control of drop size, jetting frequency, and drop spacing, solid metal traces whose conductivities match that of the bulk metal have been fabricated on temperature sensitive flexible polymer substrates. The process uses inexpensive wire, rather than nanoparticle ink, as the feedstock material. Pre and post-processing steps normally used with nanoparticle ink processes, such as substrate cleaning and ink drying + curing, are eliminated. The presentation will include examples of non-planar printing as well as 3D printed features without the need for support structures.

Bio: Denis Cormier is RIT’s Earl W. Brinkman Professor and Director of the New York State funded AMPrint Center for Advanced Technology. Dr. Cormier has worked in the area of 3D printing and related additive processes for nearly 25 years. Since joining RIT in 2009, his research has focused on technologies such as multi-material inkjet deposition, direct-write processes including aerosol printing and microdispensing, and pulsed photonic curing. Most recently, he has been focused on development of a liquid metal droplet jetting process for highly conductive flexible electronics with excellent substrate adhesion.

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4 November 2021

HP Labs

Thursday

HP 3D Printing: Metal Jet Printing and 3D Printed Electronics

More Details

2:30pm

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Talk Demo

Jarrid Wittkopf

Research Engineer

Within this talk, I will cover two items: HP’s released product of Metal Jet printing, a metal binder jet printing process, and 3D Printed Electronics with Multi Jet Fusion, a research-level activity led out of HP Labs. Our Metal Jet process is class leading on many metrics like cost and part quality, taking advantage of our decades of R&D on inkjet technology, utilizing a polymeric binder that allows for quick and clean removal during the thermal processing step. We have also leveraged many of the successful approaches used in the MIM industry to produce final metal parts at scale.
For our 3D Printed Electronics (3D PE) research, we have taken advantage of the multi-fluid capabilities of Multi Jet Fusion (MJF, HP’s Polymer 3D Print technology) process to create conductive features within polymeric parts by using a conductive agent, with print speeds and final part strengths similar to MJF. I will present on our research into creating conductive traces, vias and contacts, which can be made anywhere within the printed part. I will also cover the fabrication of active devices, like a strain gauge and USB light device, as well as present on printing of resistors and cover efforts on post-print processing for further performance optimizations.

Bio: Jarrid Wittkopf is the principal investigator for the 3D for Electronics (3D4E) Project in HP Lab’s 3D Print Lab. There he focuses on advancing the core capabilities of 3D4E project as well as investigating applications and opportunities for new business creation utilizing the 3D4E technology. Before joining HP, Jarrid finished his doctorate in chemical engineering at the University of Delaware in 2017. His PhD focused on oxygen reduction reaction catalysts for hydrogen fuel cells, electrochemistry, and nanomaterial synthesis.

All, Semiconductor Packaging

HP 3D Printing: Metal Jet Printing and 3D Printed Electronics

2:30pm

Within this talk, I will cover two items: HP’s released product of Metal Jet printing, a metal binder jet printing process, and 3D Printed Electronics with Multi Jet Fusion, a research-level activity led out of HP Labs. Our Metal Jet process is class leading on many metrics like cost and part quality, taking advantage of our decades of R&D on inkjet technology, utilizing a polymeric binder that allows for quick and clean removal during the thermal processing step. We have also leveraged many of the successful approaches used in the MIM industry to produce final metal parts at scale.
For our 3D Printed Electronics (3D PE) research, we have taken advantage of the multi-fluid capabilities of Multi Jet Fusion (MJF, HP’s Polymer 3D Print technology) process to create conductive features within polymeric parts by using a conductive agent, with print speeds and final part strengths similar to MJF. I will present on our research into creating conductive traces, vias and contacts, which can be made anywhere within the printed part. I will also cover the fabrication of active devices, like a strain gauge and USB light device, as well as present on printing of resistors and cover efforts on post-print processing for further performance optimizations.

Bio: Jarrid Wittkopf is the principal investigator for the 3D for Electronics (3D4E) Project in HP Lab’s 3D Print Lab. There he focuses on advancing the core capabilities of 3D4E project as well as investigating applications and opportunities for new business creation utilizing the 3D4E technology. Before joining HP, Jarrid finished his doctorate in chemical engineering at the University of Delaware in 2017. His PhD focused on oxygen reduction reaction catalysts for hydrogen fuel cells, electrochemistry, and nanomaterial synthesis.

Watch Demo Video
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4 November 2021

IBM

Thursday

Semiconductor Packaging Competitive Analysis: An Overview of Key Technologies Used in HPC Applications

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2:30pm

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Tom Wassick

Senior Technical Staff Member

Bio: Tom Wassick is a Senior Technical Staff Member in the Packaging Development organization within the IBM Systems Group at East Fishkill, NY. He received a B.S. degree in Biomedical Engineering in 1980 from Rensselaer Polytechnic Institute and a M.S. degree in Materials Engineering in 1982, also from Rensselaer.

In his years at IBM, he was worked in multiple technology areas all related to electronics packaging technology, most notably in the areas of thin film wiring and repair technology and laser materials processing. He is currently responsibility for electrical diagnostics and failure analysis for IBM’s chip packaging technology. Additional responsibilities include interconnect electromigration and packaging technology competitive analysis. He holds more than 40 US Patents and has numerous publications.

All, Semiconductor Packaging

Semiconductor Packaging Competitive Analysis: An Overview of Key Technologies Used in HPC Applications

2:30pm

Bio: Tom Wassick is a Senior Technical Staff Member in the Packaging Development organization within the IBM Systems Group at East Fishkill, NY. He received a B.S. degree in Biomedical Engineering in 1980 from Rensselaer Polytechnic Institute and a M.S. degree in Materials Engineering in 1982, also from Rensselaer.

In his years at IBM, he was worked in multiple technology areas all related to electronics packaging technology, most notably in the areas of thin film wiring and repair technology and laser materials processing. He is currently responsibility for electrical diagnostics and failure analysis for IBM’s chip packaging technology. Additional responsibilities include interconnect electromigration and packaging technology competitive analysis. He holds more than 40 US Patents and has numerous publications.

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4 November 2021

Poster Session

Thursday

Poster Session

More Details

3:00pm

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Talk Demo

Poster Session

3:00pm

Watch Demo Video
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5 November 2021

Defense Advanced Research Projects Agency (DARPA)

Friday

Electronic Resurgence Initiative Briefing

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10:00am

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Carl McCants

Special Assistant to the Director

The DARPA Microsystems Technology Office (MTO) Electronics Resurgence Initiative (ERI), initially announced in 2017, is a response to several technical and economic trends in the microelectronics sector. Among these trends, the rapid increase in the cost and complexity of advanced microelectronics design and manufacture is challenging a half-century of progress under Moore's Law, prompting a need for alternative approaches to traditional transistor scaling. Meanwhile, non-market foreign forces are working to shift the electronics innovation engine overseas and cost-driven foundry consolidation has limited Department of Defense (DoD) access to leading-edge electronics, challenging U.S. economic and security advantages. Moreover, highly publicized challenges to the nation's digital backbone are fostering a new appreciation for electronics security-a longtime defense concern.

ERI ensures far-reaching improvements in electronics performance well beyond the limits of traditional scaling. The programs make a significant investment to create a more specialized, secure, and automated electronics industry that serves the needs of both defense as well as the domestic commercial sectors. Building on the tradition of other successful government-industry partnerships, ERI aims to forge forward-looking collaborations among the commercial electronics community, defense industrial base, university researchers, and the DoD to address these challenges. Given today's cost, complexity, and security challenges, the nation now stands ready to collaboratively innovate the next wave of electronics progress.

Leveraging 3D heterogeneous integration, the next wave should support continuing electronics progress despite challenges to traditional silicon scaling. This integration will enable innovators to both add new materials and devices to the silicon foundation and create specialized functions precisely designed to meet the diverse needs of the commercial and defense sectors. To manage the complexity of working in three dimensions, the next wave will also demand new architectures and design tools that address rising design costs, enable rapid system upgrades, and make security integration a primary design concern.

Bio: Dr. Carl E. McCants is a special assistant to the DARPA director, focusing on the Microsystems Technology Office's (MTO) Electronics Resurgence Initiative (ERI) and the National Network for Microelectronics Research and Development.
Prior to his role at DARPA, he was the technical director of the Supply Chain and Cyber Directorate of the National Counterintelligence and Security Center (NCSC), in the Office of the Director of National Intelligence. McCants provided scientific and technical input and briefed senior government leaders on national-level supply chain integrity issues. He also provided subject matter expertise on microelectronics-related supply chain concerns.

From 2012 to 2018, McCants was a senior program manager at the Intelligence Advanced Research Projects Activity (IARPA), managing the Rapid Analysis of Various Emerging Nanoelectronics (RAVEN) program, the Trusted Integrated Chips (TIC) program, and the Circuit Analysis Tools (CAT) program. His IARPA programs earned him the Intelligence Community's Science & Technology Individual Contributor Award for FY2016.

From 2010 to 2012, he was a program manager in MTO at DARPA, focused on microelectronic integration and hardware assurance and reliability. From 2003 to 2009, he was an associate at Booz Allen Hamilton, where he served as the chief technologist to the director of MTO, and special assistant to the DARPA deputy director.

From 1999 to 2003, McCants was a project manager at Agilent Technologies' Semiconductor Products Group where he was responsible for front-end and back-end optical and electrical characterization of photonic devices, and automated test platform development. From 1988 to 1999, he was a development engineer at Hewlett-Packard's Optical Communication Division, where he focused on materials characterization, wafer fabrication, and photonic measurements of LEDs and lasers.
McCants received his bachelor's degree from Duke University in 1981 and his master's and doctoral degrees from Stanford University in 1982 and 1989, respectively, all in electrical engineering. He is a senior member of the IEEE.

All, Semiconductor Packaging

Electronic Resurgence Initiative Briefing

10:00am

The DARPA Microsystems Technology Office (MTO) Electronics Resurgence Initiative (ERI), initially announced in 2017, is a response to several technical and economic trends in the microelectronics sector. Among these trends, the rapid increase in the cost and complexity of advanced microelectronics design and manufacture is challenging a half-century of progress under Moore's Law, prompting a need for alternative approaches to traditional transistor scaling. Meanwhile, non-market foreign forces are working to shift the electronics innovation engine overseas and cost-driven foundry consolidation has limited Department of Defense (DoD) access to leading-edge electronics, challenging U.S. economic and security advantages. Moreover, highly publicized challenges to the nation's digital backbone are fostering a new appreciation for electronics security-a longtime defense concern.

ERI ensures far-reaching improvements in electronics performance well beyond the limits of traditional scaling. The programs make a significant investment to create a more specialized, secure, and automated electronics industry that serves the needs of both defense as well as the domestic commercial sectors. Building on the tradition of other successful government-industry partnerships, ERI aims to forge forward-looking collaborations among the commercial electronics community, defense industrial base, university researchers, and the DoD to address these challenges. Given today's cost, complexity, and security challenges, the nation now stands ready to collaboratively innovate the next wave of electronics progress.

Leveraging 3D heterogeneous integration, the next wave should support continuing electronics progress despite challenges to traditional silicon scaling. This integration will enable innovators to both add new materials and devices to the silicon foundation and create specialized functions precisely designed to meet the diverse needs of the commercial and defense sectors. To manage the complexity of working in three dimensions, the next wave will also demand new architectures and design tools that address rising design costs, enable rapid system upgrades, and make security integration a primary design concern.

Bio: Dr. Carl E. McCants is a special assistant to the DARPA director, focusing on the Microsystems Technology Office's (MTO) Electronics Resurgence Initiative (ERI) and the National Network for Microelectronics Research and Development.
Prior to his role at DARPA, he was the technical director of the Supply Chain and Cyber Directorate of the National Counterintelligence and Security Center (NCSC), in the Office of the Director of National Intelligence. McCants provided scientific and technical input and briefed senior government leaders on national-level supply chain integrity issues. He also provided subject matter expertise on microelectronics-related supply chain concerns.

From 2012 to 2018, McCants was a senior program manager at the Intelligence Advanced Research Projects Activity (IARPA), managing the Rapid Analysis of Various Emerging Nanoelectronics (RAVEN) program, the Trusted Integrated Chips (TIC) program, and the Circuit Analysis Tools (CAT) program. His IARPA programs earned him the Intelligence Community's Science & Technology Individual Contributor Award for FY2016.

From 2010 to 2012, he was a program manager in MTO at DARPA, focused on microelectronic integration and hardware assurance and reliability. From 2003 to 2009, he was an associate at Booz Allen Hamilton, where he served as the chief technologist to the director of MTO, and special assistant to the DARPA deputy director.

From 1999 to 2003, McCants was a project manager at Agilent Technologies' Semiconductor Products Group where he was responsible for front-end and back-end optical and electrical characterization of photonic devices, and automated test platform development. From 1988 to 1999, he was a development engineer at Hewlett-Packard's Optical Communication Division, where he focused on materials characterization, wafer fabrication, and photonic measurements of LEDs and lasers.
McCants received his bachelor's degree from Duke University in 1981 and his master's and doctoral degrees from Stanford University in 1982 and 1989, respectively, all in electrical engineering. He is a senior member of the IEEE.

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5 November 2021

Griffis AF Base

Friday

Quantum Integrated Photonics: Heterogeneous Integration in Foundry Level Devices

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10:00am

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Mike Fanto

Senior Research Physicist

Silicon integrated photonics has grown in the last decade to fill the market with classical devices that offer tremendous SWaP benefits over conventional bulk optics or fiber components. For quantum systems the material and device losses present were still too large to allow for larger scaling of systems at the single and low photon level. Over the last couple years, both industry and government laboratories have worked closely with commercial foundries to drop the optical losses to levels that now can scale quantum systems. This research area, the results, and the next steps forward for integrating other materials and qubit systems into the platform will be the subject of my talk.

Bio: Michael Fanto is a Senior Research Physicist with the Air Force Research Laboratory, Information Directorate in the Quantum Technologies Branch located in Rome, New York. He is the experimental lead for the quantum information processing group where he conducts research on quantum integrated photonics, heterogeneous qubit integration, entanglement distribution, quantum networking, and quantum information processing. He completed his BS degree in Physics from Utica College, and his Ph.D. in Microsystems Engineering focused on ultrawide-bandgap quantum integrated photonics from Rochester Institute of Technology.

All, Semiconductor Packaging

Quantum Integrated Photonics: Heterogeneous Integration in Foundry Level Devices

10:00am

Silicon integrated photonics has grown in the last decade to fill the market with classical devices that offer tremendous SWaP benefits over conventional bulk optics or fiber components. For quantum systems the material and device losses present were still too large to allow for larger scaling of systems at the single and low photon level. Over the last couple years, both industry and government laboratories have worked closely with commercial foundries to drop the optical losses to levels that now can scale quantum systems. This research area, the results, and the next steps forward for integrating other materials and qubit systems into the platform will be the subject of my talk.

Bio: Michael Fanto is a Senior Research Physicist with the Air Force Research Laboratory, Information Directorate in the Quantum Technologies Branch located in Rome, New York. He is the experimental lead for the quantum information processing group where he conducts research on quantum integrated photonics, heterogeneous qubit integration, entanglement distribution, quantum networking, and quantum information processing. He completed his BS degree in Physics from Utica College, and his Ph.D. in Microsystems Engineering focused on ultrawide-bandgap quantum integrated photonics from Rochester Institute of Technology.

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5 November 2021

NSWC Crane Division

Friday

Interconnect Technologies (Printed Circuit Boards) Required to Support Microelectronics Packaging in DoD

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10:00am

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Roger Smith

DoD Executive Agent for Printed Circuit Board and Interconnect Technologies

This presentation will provide an overview of DoD Executive Agent (EA) efforts promoting printed circuit board and interconnect technology (PrCB) development projects leveraging domestically sourced materials and processes to address the most advanced circuit board and microelectronics packaging requirements. The presentation will also offer insights into related DoD policy and guidance development efforts designed to promote the acquisition and sustainment of electronic systems required to provide US Warfighters with unrivaled electronic systems.

Today's military systems rely heavily on electronics to complete their intended missions, and Interconnect Technologies are a critical and integral part of those electronics. Over the last 40 years the U.S. printed circuit board manufacturing industry has steadily declined, as an increasing number of facilities closed, merged with other companies, or moved offshore. This has exposed the Department to vulnerabilities accessing critical Interconnect Technology products. Additionally, recent and ongoing Covid-19 pandemic impacts have exacerbated and highlighted supply chain impacts that further exposed vulnerabilities within this industry sector.

DoD has become reliant on foreign, and sometimes undependable suppliers to deliver advanced technology products. The DoD PrCB EA, via DoD Directive 5101.18E, was chartered to facilitate access to reliable, trusted, and affordable products and technologies that meet the quality, performance, and security requirements of the DoD. The EA is facilitating collaboration within and across the DoD to conduct research, development, and sustainment efforts targeting component-unique requirements.

This presentation will update the audience on DoD Executive Agent progress towards achieving it’s mission to ensure DoD access to trusted and affordable electronic interconnect technologies necessary for critical national defense systems and warfighter superiority.

Bio: Mr. Smith entered public service at Naval Surface Warfare Center Crane Division in October 1987 serving in both project technical and leadership positions throughout his tenure. In July of 2015 Mr. Smith accepted his current assignment as the DoD Executive Agent for Printed Circuit Board and Interconnect Technologies - Navy Technical Lead. In this role, he supports initiatives to oversee issues related to Trust, Technology Development, Supply Chain Management, and Knowledge and Capability Sustainment. As a collateral and complementary duty, Mr. Smith also currently serves as the Naval Sea Systems Command, Technical Warrant Holder for Electronics.

Mr. Smith holds a Bachelor’s Degree in Mechanical Engineering from Purdue University, a Master’s Degree in Public Affairs from the Indiana University School of Public and Environmental Affairs, and is Level III certified in the Defense Acquisition Workforce - Systems, Production, Research and Engineering career field.

All, Semiconductor Packaging

Interconnect Technologies (Printed Circuit Boards) Required to Support Microelectronics Packaging in DoD

10:00am

This presentation will provide an overview of DoD Executive Agent (EA) efforts promoting printed circuit board and interconnect technology (PrCB) development projects leveraging domestically sourced materials and processes to address the most advanced circuit board and microelectronics packaging requirements. The presentation will also offer insights into related DoD policy and guidance development efforts designed to promote the acquisition and sustainment of electronic systems required to provide US Warfighters with unrivaled electronic systems.

Today's military systems rely heavily on electronics to complete their intended missions, and Interconnect Technologies are a critical and integral part of those electronics. Over the last 40 years the U.S. printed circuit board manufacturing industry has steadily declined, as an increasing number of facilities closed, merged with other companies, or moved offshore. This has exposed the Department to vulnerabilities accessing critical Interconnect Technology products. Additionally, recent and ongoing Covid-19 pandemic impacts have exacerbated and highlighted supply chain impacts that further exposed vulnerabilities within this industry sector.

DoD has become reliant on foreign, and sometimes undependable suppliers to deliver advanced technology products. The DoD PrCB EA, via DoD Directive 5101.18E, was chartered to facilitate access to reliable, trusted, and affordable products and technologies that meet the quality, performance, and security requirements of the DoD. The EA is facilitating collaboration within and across the DoD to conduct research, development, and sustainment efforts targeting component-unique requirements.

This presentation will update the audience on DoD Executive Agent progress towards achieving it’s mission to ensure DoD access to trusted and affordable electronic interconnect technologies necessary for critical national defense systems and warfighter superiority.

Bio: Mr. Smith entered public service at Naval Surface Warfare Center Crane Division in October 1987 serving in both project technical and leadership positions throughout his tenure. In July of 2015 Mr. Smith accepted his current assignment as the DoD Executive Agent for Printed Circuit Board and Interconnect Technologies - Navy Technical Lead. In this role, he supports initiatives to oversee issues related to Trust, Technology Development, Supply Chain Management, and Knowledge and Capability Sustainment. As a collateral and complementary duty, Mr. Smith also currently serves as the Naval Sea Systems Command, Technical Warrant Holder for Electronics.

Mr. Smith holds a Bachelor’s Degree in Mechanical Engineering from Purdue University, a Master’s Degree in Public Affairs from the Indiana University School of Public and Environmental Affairs, and is Level III certified in the Defense Acquisition Workforce - Systems, Production, Research and Engineering career field.

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5 November 2021

NSWC Crane Division

Friday

State-Of-The-Art Heterogeneous Integrated Packaging (SHIP) Program

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10:00am

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Darren Crum

Leading Microelectronics Advanced Packaging

For over a decade it has been a challenge for the Department of Defense (DoD) to engage in State-of-the-art (SOTA) microelectronics access beyond utilizing COTS chips. The current industry trend toward chiplets and 3D packaging represents a paradigm shift offering the DoD a unique opportunity. The DoD State Of The Art (SOTA) Heterogeneous Integrated Packaging (SHIP) program goal is to develop and validate a sustainable and scalable model for access to SOTA microelectronics packaging of customized DoD microelectronic devices produced using a standard commercial assembly, packaging, and test flow.

Bio: Dr. Crum began his career with the Department of the Navy (DoN) at Naval Surface Warfare Center, Crane Division. Early in his career he managed three microelectronics focused engineering branches, including the Component Engineering Branch, the Obsolescence Management Branch, and the Electronics Design Branch.

In 2006, Dr. Crum became the Naval Sea Systems (NAVSEA) Command Anti-Tamper Technical Warrant Holder, and then in 2009 he became the DoN Anti-Tamper Technology Coordinator. In this role, he focused on identifying technical gaps and leading the development of new technologies to protect microelectronics.

In 2021, Dr. Crum became the Microelectronics Advanced Packaging & Test Lead and the Technical Lead of the SOTA Heterogeneous Integrated Packaging (SHIP) program for OUSD(R&E) – Modernization Microelectronics. In this role, he is responsible for executing technology development efforts to support the DoD Microelectronics Roadmap.

Dr. Crum has a BSEE (1990) from the University of Kentucky, a MA (2000) in Public Administration from Indiana University, and a doctorate (2006) in Organization & Management from Capella University.

All, Semiconductor Packaging

State-Of-The-Art Heterogeneous Integrated Packaging (SHIP) Program

10:00am

For over a decade it has been a challenge for the Department of Defense (DoD) to engage in State-of-the-art (SOTA) microelectronics access beyond utilizing COTS chips. The current industry trend toward chiplets and 3D packaging represents a paradigm shift offering the DoD a unique opportunity. The DoD State Of The Art (SOTA) Heterogeneous Integrated Packaging (SHIP) program goal is to develop and validate a sustainable and scalable model for access to SOTA microelectronics packaging of customized DoD microelectronic devices produced using a standard commercial assembly, packaging, and test flow.

Bio: Dr. Crum began his career with the Department of the Navy (DoN) at Naval Surface Warfare Center, Crane Division. Early in his career he managed three microelectronics focused engineering branches, including the Component Engineering Branch, the Obsolescence Management Branch, and the Electronics Design Branch.

In 2006, Dr. Crum became the Naval Sea Systems (NAVSEA) Command Anti-Tamper Technical Warrant Holder, and then in 2009 he became the DoN Anti-Tamper Technology Coordinator. In this role, he focused on identifying technical gaps and leading the development of new technologies to protect microelectronics.

In 2021, Dr. Crum became the Microelectronics Advanced Packaging & Test Lead and the Technical Lead of the SOTA Heterogeneous Integrated Packaging (SHIP) program for OUSD(R&E) – Modernization Microelectronics. In this role, he is responsible for executing technology development efforts to support the DoD Microelectronics Roadmap.

Dr. Crum has a BSEE (1990) from the University of Kentucky, a MA (2000) in Public Administration from Indiana University, and a doctorate (2006) in Organization & Management from Capella University.

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5 November 2021

US Army Research Laboratory

Friday

PM NextFlex Manufacturing Institute, ARL-ERP 3D Hybrid Electronics Thrust Leads

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10:00am

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Eric Forsythe

Team Leader for Flexible Electronics

The presentation will highlight ongoing public-private partnerships developing advanced hybrid electronic manufacturing. The manufacturing progress from NextFlex Manufacturing Institute and members will be presented for flexible hybrid electronics and unique hybrid electronic packaging. The presentation will highlight key examples of technology demonstrations for wearables, x-ray imaging, and communications.

Bio: Eric W. Forsythe, Ph.D is the Team Leader for Flexible Electronics at the US Army Research Laboratory, Adelphi, MD. His responsibilities include; the Program Manager for the Flexible Hybrid Electronics Manufacturing Innovation Institute. Recently, Dr Forsythe was the Deputy Program Manager for the U.S. Army’s Flexible Display Center that demonstrated the World’s Largest flexible organic ligtht emitting diode displays and most recently the World’s Largest flexible digital x-ray imagers for DOD Explosive Ordnance Disposal. Additional responsibilities include the co-PI with the human performancde team for the ARL initiaitive “Continuous, Real-Time Assessment of Soldiers:The Foundation for Future Individualized and Adaptive Technologies” and the ARL Directors Initiative entitle “Ultrafast Electron Spectrocopy” for unique materials science exploration. Prior to joining ARL in 2001, Dr Forsythe was a Research Associate at the University of Rochester where he worked on electronic interfaces in organic light emitting diodes (OLEDs) with Eastman Kodak, the inventors of the commercial OLED display technology. In 1996, Dr Forsythe received his Ph.D in Engineering Physics at Stevens Institute of Technology. He has spent time working at small businesses on SBIR-projects in wide range of technologies and at Kearfott Guidance and Navigation on the Trident Missile stellar inertial guidance system, in the mid-1980’s. Dr Forsythe has more than 60 publications (2000 citations, H-index 19), and 5 patents filed or issued.

All, Semiconductor Packaging

PM NextFlex Manufacturing Institute, ARL-ERP 3D Hybrid Electronics Thrust Leads

10:00am

The presentation will highlight ongoing public-private partnerships developing advanced hybrid electronic manufacturing. The manufacturing progress from NextFlex Manufacturing Institute and members will be presented for flexible hybrid electronics and unique hybrid electronic packaging. The presentation will highlight key examples of technology demonstrations for wearables, x-ray imaging, and communications.

Bio: Eric W. Forsythe, Ph.D is the Team Leader for Flexible Electronics at the US Army Research Laboratory, Adelphi, MD. His responsibilities include; the Program Manager for the Flexible Hybrid Electronics Manufacturing Innovation Institute. Recently, Dr Forsythe was the Deputy Program Manager for the U.S. Army’s Flexible Display Center that demonstrated the World’s Largest flexible organic ligtht emitting diode displays and most recently the World’s Largest flexible digital x-ray imagers for DOD Explosive Ordnance Disposal. Additional responsibilities include the co-PI with the human performancde team for the ARL initiaitive “Continuous, Real-Time Assessment of Soldiers:The Foundation for Future Individualized and Adaptive Technologies” and the ARL Directors Initiative entitle “Ultrafast Electron Spectrocopy” for unique materials science exploration. Prior to joining ARL in 2001, Dr Forsythe was a Research Associate at the University of Rochester where he worked on electronic interfaces in organic light emitting diodes (OLEDs) with Eastman Kodak, the inventors of the commercial OLED display technology. In 1996, Dr Forsythe received his Ph.D in Engineering Physics at Stevens Institute of Technology. He has spent time working at small businesses on SBIR-projects in wide range of technologies and at Kearfott Guidance and Navigation on the Trident Missile stellar inertial guidance system, in the mid-1980’s. Dr Forsythe has more than 60 publications (2000 citations, H-index 19), and 5 patents filed or issued.

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5 November 2021

Panel Discussion

Friday

Panel Discussion

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11:20pm

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Talk Demo

Panel Discussion

11:20pm

Watch Demo Video
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5 November 2021

GE Research

Friday

Energy Storage: The Next Big Thing – 200 years in the making.

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12:00pm

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Ahmed Elasser

Principal Systems Engineer

Energy Storage has been in the making for at least two hundred years, but it has recently been playing a prominent role with the advent of highly variable and intermittent renewable resources such as wind and solar. In addition to providing an overview of Energy Storage Technologies in general, Battery Energy Storage Systems (BESS) will be addressed from a cell, module, string, power conversion, and grid level point of view. Key challenges and future opportunities for innovation in the BESS space will also be discussed. A comprehensive reference list will also be provided.

Bio: Ahmed Elasser received his MS & PhD degrees in Electric Power & Power Electronics in 1993 & 1996 respectively from Rensselaer Polytechnic Institute. He is a Principal Systems Engineer at GE Research in the areas of Electric Power, Power Electronics, and Power Semiconductor Devices. He worked on Power Devices, Solar Energy, Power Conversion Systems, and is currently leading the Battery Energy Storage Systems Power Conversion. He published over 40 papers and has 36 issued patents. He is a Senior IEEE Member. Dr. Elasser is the recipient of numerous GE Awards for his contributions and innovations over his 26 years GE career.

All, Semiconductor Packaging, Batteries and Fuel Cells, Energy Storage, Advanced Materials

Energy Storage: The Next Big Thing – 200 years in the making.

12:00pm