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Marc Verschuuren

Director & Chief Technology Officer

SCIL Nanoimprint solutions

Netherlands

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Waferscale nanoimprint with ultra-low distortions for wafer-scale MicroLED integration

Printed Electronics Innovation Day | Winter 2024

Display Innovation Day | Winter 2024

10 December 2024

Online

TechBlick Platform

Achieving high efficiency MicroLED based micro- and pico-displays still has many challenges. With desired pixel sizes below 5 micron this leads to significant challenges in re-combination to RGB display chips and low LED efficiency due to the large surface ratio of the LED chip edges to the LED emission area. It is possible to produce / grow an all nitride RGB LED chips by nano-patterned templated growth on a single wafer, e.g. nano-wire LEDs. This would eliminate the re-combination steps and increase LED efficiency due to damage free LED edges. To do so, there is a need to accurately pattern sub-50nm patterns with less than 1nm size variation and overlay alignment of ~ 500nm, preferably sub-100nm, on a wafer that is bowed and not flat anymore due to topology from previous LED growth runs. Accurate placement of the sub-pixels on the epi-wafer is also required when the LED chips are bonded to the driver IC’s. Any pattern distortions will add to potential losses due to bad connections. Conventional (deep) UV lithography uses light to define patterns and is therefore limited by the diffraction limit and related critical depth of focus issue. Nanoimprint lithography, or NIL, uses a physical process of a stamp that has the pattern information coded into it in height / depth. On stamp contact with the wafer, liquid resist will flow into the nano-features before hardening into a 3D inverse shape of the stamp. NIL therefore is not limited by the diffraction limit and can faithfully replicate complex shapes and features with sub-10nm resolution. The disadvantage with NIL is that intimate physical contact needs to be made over the whole wafer. To allow this, the industry has moved to stamps that are flexible in order to accommodate for wafer bow, thickness variations and topology. However, the flexibility of the stamp hinders the overlay alignment accuracy. We’ll demonstrate that by using the proper processes for stamp fabrication, the NIL step, stamp release and resist material systems, we are able to achieve sub-500nm overlay alignment over full 300mm wafers and show the potential to reach sub-100nm overlay alignment.

Watch the 5-minute excerpt from the talk
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