Economic and Environmental Perspectives on Panel Level Packaging

Bio: Dr. Mathilde Billaud is a research fellow at Fraunhofer IZM since 2017. Between 2013 and 2016, she conceived a process flow in the 300mm-Silicon clean room of CEA-Leti (Grenoble, France) integrating III-V materials in CMOS transistors. She is now involved in an industrial consortium organized by Fraunhofer IZM, on Fan-Out Panel Level Packaging to model the complete process flows related to the different technology options for chip packaging on panel size developed at IZM. The modeling enables a combined cost and environmental assessment. This methodology is now transferred to other research and industrial projects. She is also part of the consortium that evaluates the requests for exemption to the restriction of hazardous substances (RoHS) directive and for the end of life vehicles directive (ELV directive) with a focus on lead-acid batteries. Her favorite research topics cover critical materials, resource and energy consumption, as well as circular practices in microelectronic manufacturing. She holds a Master’s degree from the National Graduate School of Chemistry of Montpellier (France) with an expertise in chemistry and chemical engineering. She received a doctor’s degree in 2017 for her thesis “Integration of III-V materials as high mobility channel for MOSFET transistor”.