Challenges for upscaling Perovskite/Silicon tandem solar cells

The crystalline Silicon (c-Si) / Perovskite (PK) 2 terminal (2T) Tandem solar cells have
recently reached a certified power conversion efficiency of 34.9% [1], exceeding the
theoretical limit of silicon single junction. This makes this tandem a good growth driver for
the PV technology. Those results are really promising but are still obtained at lab scale on
small size devices (≤1cm²), the Perovskite technology being less mature than the well-
established Silicon one.
Even if demonstrations on larger cells or modules are becoming more and more numerous,
several challenges remain in order to upscale the materials and the processes toward the
industry. In order to reduce the time to market of this new technology,
This work ultimate goal is then to develop efficient and stable Silicon-Perovskite (Si-PK)
tandem devices that can be manufactured with techniques compatible with the nextgen PV
industry.
Starting from ~9 cm² devices with PIN architectures, with PCE above 30%, the CEA is trying
to develop materials and processes compatible with industrial requirements. Several
bottlenecks are identified and will be discussed among the upscaling of interface layers or
Perovskite’s one on textured Cz silicon wafers, the development of low temperature screen printing
process, the long term stability of encapsulated Tandem cells…..