Eason Peng | VIEWTRIX Technology Co., Ltd: What fundamental display technology shift is driving the pursuit of lightweight VR headsets, and what are its core enablers?
05:07 - 06:21
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What fundamental display technology shift is driving the pursuit of lightweight VR headsets, and what are its core enablers?
The VR headset market is undergoing a significant display technology transition, moving from FSLCD, as seen in devices like Meta Quest 3, to Micro-OLED, exemplified by the Apple Vision Pro. While FSLCD offered a PPD (Pixels Per Degree) of approximately 20 degrees, the adoption of Micro-OLED in the Vision Pro doubled this to 36 degrees, enhancing visual fidelity. However, this improvement came with drawbacks, notably increased weight and higher manufacturing costs, presenting a challenge for broader consumer adoption.
The future trajectory for VR headsets is focused on achieving lightweight designs, as demonstrated by prototypes like the Panasonic device at CES, which boasts a 70-degree FOV with a PVD similar to the Vision Pro, yet weighs only 115 grams. Key parameters enabling this lightweight design include a smaller panel size, which necessitates a smaller pixel pitch to maintain or improve PPD. Additionally, cost reduction and optimized power consumption, allowing for smaller batteries, are critical for widespread market acceptance of these advanced, lightweight VR systems.
In this short video, you can learn:
* The evolution of VR display technology from FSLCD to Micro-OLED.
* The trade-offs in PPD, weight, and cost associated with current VR display technologies.
* The critical technical parameters for achieving lightweight VR headsets, including panel size, pixel pitch, cost, and power consumption.
📋 **Clip Abstract** This clip analyzes the shift in VR display technology from FSLCD to Micro-OLED, highlighting the benefits in PPD and the challenges of increased weight and cost. It then outlines the key technical enablers for future lightweight VR headsets, focusing on smaller panel size, pixel pitch, cost, and power efficiency.
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#MicroOLED, #FSLCD, #PixelPitch, #PPD, #VRHeadsets, #SemiconductorDisplays
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Micro-OLED design for AR/VR application
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00:18 - 01:08
How does a fabless design house achieve market leadership in self-emission display driver ICs and Micro-OLED silicon?
How does a fabless design house achieve market leadership in self-emission display driver ICs and Micro-OLED silicon?
RES Technology operates as a fabless design house, specializing in display driver ICs for self-emission materials and Micro-OLED silicon. The company has achieved significant market penetration, with over 130 million display driver ICs shipped between 2020 and 2024, establishing it as a leading provider in the China market. For Micro-OLED, RES Technology has shipped approximately 30,000 wafers, equivalent to 5 million micro display sets, positioning itself as a unique entity solely focused on Micro-OLED silicon design, unlike integrated manufacturers such as Sony.
This specialized focus allows RES Technology to collaborate extensively with major display manufacturers like BOE, Visionox, CSOT, and EDO for its driver IC products, and with CI and BOE for Micro-OLED. The company's strategy emphasizes silicon membrane design, providing core technology to partners who handle the subsequent fabrication and module integration. This distinct business model underpins its substantial market share and influence within the display industry.
In this short video, you can learn:
* RES Technology's dual product pillars: display driver ICs and Micro-OLED silicon.
* The company's market leadership in China for driver ICs and its unique focus on Micro-OLED silicon design.
* Key shipment figures and strategic partnerships within the display industry.
📋 **Clip Abstract** This clip introduces RES Technology as a leading fabless design house specializing in display driver ICs and Micro-OLED silicon. It highlights the company's market achievements and unique business model focused on silicon membrane design.
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#SelfEmissionDriverICs, #MicroOLEDsilicon, #SiliconMembraneDesign, #FablessDesignHouse, #ARVRDisplays, #WearableTech
07:06 - 12:01
What are the primary silicon process and architectural challenges in achieving ultra-small pixel pitches and cost-effective Micro-OLED displays for lightweight VR?
What are the primary silicon process and architectural challenges in achieving ultra-small pixel pitches and cost-effective Micro-OLED displays for lightweight VR?
Achieving smaller pixel pitches for lightweight VR displays, targeting display sizes from 0.7 to 1.1 inches with resolutions of 2400x2200 to 3200x3200, presents several silicon process limitations. The primary challenges include device pitch and leakage current, which significantly impact the minimum achievable pixel pitch, especially when implementing in-pixel compensation for micro-OLEDs. Furthermore, metal routing becomes critical; maintaining a consistent voltage on the storage capacitor within a reduced pixel area necessitates a higher capacitor density. Advanced process nodes can mitigate these issues by offering smaller device sizes and lower leakage, thereby reducing the required capacitor density per pixel.
Cost optimization is another crucial factor, particularly concerning the display architecture. Micro-OLEDs can be designed with either a one-chip solution, where pixel circuits and drivers are integrated, or a two-chip solution, separating the display and driver ICs. While a one-chip design can offer a 10% higher die per wafer compared to a two-chip solution for smaller displays, the two-chip approach often becomes more cost-effective for larger Micro-OLEDs (e.g., above 0.9 inches). This is because the two-chip design allows for a reduction in the front-end layers of the display wafer, leading to lower overall silicon plan costs despite requiring additional space for bonding the separate driver IC.
In this short video, you can learn:
* The technical challenges in silicon process and metal routing for achieving smaller pixel pitches in Micro-OLEDs.
* How capacitor density and advanced process nodes influence pixel design and performance.
* The cost implications and trade-offs between one-chip and two-chip architectures for Micro-OLED displays.
📋 **Clip Abstract** This clip details the technical hurdles in miniaturizing Micro-OLED pixels, focusing on silicon process limitations, metal routing, and capacitor density requirements. It also explores the cost-effectiveness of one-chip versus two-chip display architectures, highlighting their respective advantages based on display size.
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#MicroOLEDPixelDesign, #SiliconProcessChallenges, #CapacitorDensityOptimization, #DisplayArchitectureCost, #VRDisplays, #ImmersiveExperiences