Eason Peng | VIEWTRIX Technology Co., Ltd: Why does sub-5-micron pixel pitch in Micro-OLED force a complete rethink of silicon capacitor design?
07:48 - 09:47
Other snippets from this talk
Summary of the clip:
How do we overcome the physical and electrical scaling limits of silicon backplanes as micro-LED pixel pitches shrink below five microns?
As micro-display pixel pitches shrink, backplane designers face severe silicon process limitations within the CMOS drive circuitry. Unlike larger displays that rely on external optical Demura systems, micro-arrays require in-pixel compensation circuits to ensure luminance uniformity. This demand for in-pixel compensation forces designers to pack more active devices into a single pixel, meaning that device pitch and sub-threshold leakage currents ultimately dictate the minimum achievable pixel pitch.
Interconnect routing and charge preservation present additional engineering bottlenecks when scaling down these micro-pixel architectures. To maintain a stable driving voltage on the storage capacitor during the frame time, the capacitance density must be scaled up aggressively as the physical pixel area shrinks. Designers must transition to advanced capacitor architectures, such as MIM (Metal-Insulator-Metal) or MOM (Metal-Oxide-Metal) configurations, to sustain the necessary capacitance within a highly restricted footprint.
The selection of the silicon process node directly influences these capacitor integration strategies and their physical limits. For instance, utilizing a MOM capacitor configuration can successfully enable pixel pitches in the range of 4.5 to 5.5 microns. Furthermore, migrating to more advanced foundry process nodes relaxes the strict capacitance density requirements, as reduced via dimensions and optimized design rules mitigate the layout constraints inherent to legacy nodes.
In this short video, you can learn:
* The critical role of in-pixel compensation circuits in micro-arrays and how they limit physical pixel scaling compared to optical Demura methods.
* The electrostatic challenges of maintaining storage capacitance values as pixel pitches shrink, and the resulting demand for high-density capacitor designs.
* How the choice of semiconductor process node and capacitor architecture (MOM vs. MIM) directly impacts the achievable pixel pitch and layout density.
π **Clip Abstract** The speaker discusses the primary silicon backplane challenges associated with scaling down micro-array pixel pitches, focusing on the need for in-pixel compensation devices and the resulting leakage and layout constraints. He explains how capacitance density must increase as pixel pitch decreases, comparing MOM and MIM capacitor designs across different semiconductor process nodes.
π€ Speaker: Eason Peng
π’ Company: VIEWTRIX Technology Co., Ltd
π
Event: AR/VR Connect 2025
π Location: Conference Centre, High Tech Campus, Eindhoven, Netherlands
π Learn more at the next TechBlick event: https://www.techblick.com
#MicroOLED, #MIMCapacitors, #InPixelCompensation, #SiliconBackplane, #Microdisplays, #ARVRHardware
This is a highlight of the presentation:
Micro-OLED design for AR/VR application
More Highlights from the same talk.
09:58 - 12:32
Is the industry's rush toward two-chip Micro-OLED architectures actually costing more for smaller displays?
Is the industry's rush toward two-chip Micro-OLED architectures actually costing more for smaller displays?
Micro-OLED display designs are split between integrated one-chip and split two-chip architectures. In a one-chip design, pixel circuitry and display drivers are embedded on a single silicon die. This eliminates the extra 3mm of routing and bonding margin required by two-chip FPC connections, yielding a highly compact form factor.
However, two-chip designs allow designers to separate the complex pixel array from the driver IC, reducing the number of front-end-of-line (FEOL) lithography layers needed on the display substrate. This creates a critical cost crossover point at a display size of approximately 0.9 inches.
For micro-displays larger than 0.9 inches, the two-chip architecture becomes highly cost-effective due to wafer yield dynamics. Conversely, for ultra-compact lightweight VR headsets targeting displays smaller than 0.9 inches, shrinking to a one-chip layout reduces overall silicon area and cuts costs by roughly 20 percent when scaling from 0.9 to 0.7 inches.
In this short video, you can learn:
* The spatial and cost differences between one-chip and two-chip Micro-OLED routing architectures.
* How the 0.9-inch display threshold acts as a financial crossover point for silicon-backplane design.
* The economic advantages of shrinking displays down to 0.7 inches for next-generation lightweight VR headsets.
π **Clip Abstract** Eason Peng explains the architectural tradeoffs between one-chip and two-chip Micro-OLED layouts for VR. He identifies a critical 0.9-inch threshold where smaller display scaling maximizes cost efficiency on silicon backplanes.
#MicroOLED, #SiliconBackplanes, #FEOLlithography, #DisplayDriverIC, #MicroDisplays, #NearEyeDisplays
14:11 - 16:02
How does ultra-low silicon leakage current enable Micro-OLEDs to slash power consumption by two-thirds?
How does ultra-low silicon leakage current enable Micro-OLEDs to slash power consumption by two-thirds?
Display power consumption in AR/VR headsets is dominated by digital data transmission and pixel driving. By implementing foveated rendering at the interface level, system designers can transmit lower-resolution peripheral data and perform upscaling on-chip, cutting digital processing power requirements in half.
For static or slow-moving content, further power savings are unlocked via dynamic frame rate switching. By dynamically dropping the display refresh rate from 110Hz to as low as 10Hz, driver power consumption can be systematically slashed to just one-third of peak levels.
However, operating at ultra-low refresh rates without visible flicker or brightness decay requires extreme leakage current control in the pixel circuit. By engineering a custom silicon backplane with highly stable pixel transistors, the storage voltage is preserved with less than a 1% luminance drop over extended frame times.
In this short video, you can learn:
* How foveated transmission and on-die upscaling reduce digital processing power by 50 percent.
* The mechanism behind dynamic frame rate scaling from 110Hz down to 10Hz for static VR/AR scenes.
* Why minimizing transistor leakage current is the primary hardware enabler for low-refresh-rate display stability.
π **Clip Abstract** Eason Peng outlines strategies for minimizing power consumption in VR and AR micro-displays. He demonstrates how coupling foveated upscaling with low-leakage dynamic refresh rate control slashes system power while preserving image stability.
#MicroOLED, #LowLeakageSilicon, #FoveatedTransmission, #DynamicRefreshRate, #Microdisplays, #NearEyeDisplays