Elias Torres Alonso | Graphenea: How do we integrate graphene at the backend-of-line without breaking CMOS compatibility or ruining device yield?
08:40 - 10:18
Other snippets from this talk
Summary of the clip:
How do we integrate graphene at the backend-of-line without breaking CMOS compatibility or ruining device yield?
At the backend-of-line (BEOL), integrating graphene requires highly customizable processing flows that respect industrial semiconductor standards. Graphenea's GFAB services bridge this gap by offering weekly production of up to 1,000 square centimeters of patterned graphene. The foundry supports various metallization schemes, including chrome-gold for general testing, nickel-aluminum for strict CMOS-compatibility, and aluminum for superconducting applications.
Beyond contact choice, the platform enables advanced passivation using alumina or polymers, alongside precision-etched vias to access channel regions and metal pads. This level of fabrication matureness allows product developers to capture immediate economies of scale. Simply scaling down the die size from a standard 10x10 mm square to 2.5x2.5 mm yields up to 16 times more devices per wafer for the same processing cost.
In this short video, you can learn:
* How to adapt graphene contact metallization using Ni-Al for CMOS compliance or pure Aluminum for superconducting circuits
* The fabrication steps involved in encapsulating graphene with alumina and opening contact vias
* How reducing die sizes scales device yield up to 16x without escalating backend processing costs
📋 **Clip Abstract** Elias Torres Alonso details Graphenea's GFAB service for custom back-end-of-line (BEOL) integration of graphene on semiconductor wafers. He highlights CMOS-compatible metallization flows, alumina passivation, and the economics of scale achieved through die size reduction.
#BeolGraphene, #CmosCompatibleMetallization, #AluminaPassivation, #DieSizeScaling, #GrapheneFoundry, #WaferScaleIntegration
This is a highlight of the presentation:
More Highlights from the same talk.
05:07 - 06:56
How can we scale graphene-based biosensors to detect complex biological footprints in liquid environments?
How can we scale graphene-based biosensors to detect complex biological footprints in liquid environments?
Graphenea's S2X series represents a major step forward for GFETs optimized specifically for liquid and biosensing applications. The architecture introduces dielectrics or polymeric passivations to isolate contacts from wet environments while offering multiple channel configurations. With options like the S20 providing 12 independent channels, developers can perform signal multiplexing to feed rich datasets into machine learning algorithms.
For advanced diagnostics, the parallel-connected S21 increases current to the milliamp range for easy integration with standard off-the-shelf silicon electronics. Meanwhile, the S22 partitions channels into four distinct quadrants, allowing four different antibodies or aptamers to be functionalized simultaneously on a single chip. This layout yields a comprehensive, multi-marker analytical footprint of a disease from a single droplet.
In this short video, you can learn:
* How contact passivation and polymer coatings enable stable GFET operations in wet environments
* The difference between multi-channel multiplexing and parallel channel configurations for raw signal averaging
* How to configure a quadrant-based chip layout to monitor multiple disease biomarkers simultaneously
📋 **Clip Abstract** This clip breaks down Graphenea's S2X series of GFET devices tailored for liquid environments and advanced biosensing. Head of Foundry Elias Torres Alonso explains how multi-channel, parallel, and quadrant-based configurations optimize signal acquisition and enable multiplexed biomarker detection.
#GrapheneFET, #ContactPassivation, #MultiplexedBiosensing, #GrapheneBiosensors, #LabOnAChip, #Bioelectronics
14:14 - 15:15
Why is the semiconductor fabrication route superior to screen printing for scaling 2D material devices?
Why is the semiconductor fabrication route superior to screen printing for scaling 2D material devices?
When evaluating manufacturing methods for 2D devices, there is a fundamental split between printed electronics and traditional semiconductor processing. While screen printing techniques offer low-cost, high-throughput patterning, they fundamentally limit the spatial resolution and long-term reliability of 2D material devices. The printing process introduces variations in flake distribution, leading to poorer device-to-device reproducibility and degraded sensitivity.
In contrast, employing semiconductor-grade lithography and transfer processes preserves the intrinsic high performance of single-layer graphene. Miniaturization can be driven down to the micron and sub-micron scale without sacrificing electrical properties. By using wafer-scale semiconductor fabrication, device developers trade raw material simplicity for high reliability, tight distribution metrics, and consistent high sensitivity.
In this short video, you can learn:
* The fundamental technical trade-offs between screen printing and semiconductor manufacturing for 2D material devices
* Why screen printing degrades the reliability and sensitivity of graphene field-effect transistors
* How semiconductor-grade miniaturization delivers high device-to-device uniformity at the micro-scale
📋 **Clip Abstract** In this Q&A segment, Elias Torres Alonso discusses why Graphenea utilizes semiconductor manufacturing instead of screen printing. He explains the trade-offs in reliability, sensitivity, and miniaturization that make wafer-scale lithography crucial for commercial 2D electronics.
#GrapheneFieldEffectTransistors, #WaferScaleLithography, #2DMaterials, #SemiconductorFabrication, #GrapheneElectronics, #PrintedElectronics