Kris Erickson | Meta: Is two-photon micro-printing the ultimate solution to the optical chip-to-fiber packaging bottleneck?
00:10:24 - 00:10:56
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Is two-photon micro-printing the ultimate solution to the optical chip-to-fiber packaging bottleneck?
Silicon photonics and high-bandwidth optical computing face a severe assembly bottleneck: aligning and interconnecting optical chips to output fibers with sub-micron accuracy. Traditional physical fiber coupling is expensive, mechanically sensitive, and limits the packaging density of high-speed co-packaged optics.
To solve this, additive manufacturing leverages ultra-high-resolution two-photon polymerization (2PP). This precise 3D lithography technique allows engineers to print specialized optical polymers directly on top of active photonic chips, effectively creating the optical equivalent of an electrical wire bond.
These 3D micro-printed waveguides bridge the physical gap between on-chip laser sources and external fiber arrays. By bypassing classical mechanical alignment limits, this approach enables compact, low-loss, and high-yield optical compute packages suitable for next-generation data centers and AI accelerators.
In this short video, you can learn:
* Why physical fiber-to-chip alignment acts as the primary barrier to high-bandwidth optical compute packaging.
* How two-photon polymerization (2PP) prints sub-micron 3D polymer structures directly on active silicon.
* The mechanics of "optical wire bonding" as an alternative to traditional optical interconnect assemblies.
š **Clip Abstract**
Kris Erickson details a novel application of additive manufacturing for optical compute packaging. By using two-photon polymerization, engineers can print optical wire bonds that solve the high-bandwidth chip-to-fiber coupling bottleneck.
#TwoPhotonPolymerization, #OpticalWireBonding, #SiliconPhotonics, #3DPrintedWaveguides, #CoPackagedOptics, #PhotonicPackaging
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00:02:19 - 00:03:43
Can additive manufacturing resolve the paradox of scaling sub-micron features without sacrificing high-volume throughput?
Can additive manufacturing resolve the paradox of scaling sub-micron features without sacrificing high-volume throughput?
Selecting the correct Additive Manufactured Electronics (AME) method is a multi-dimensional challenge dictated by a strict decision matrix of conductor deposition, substrate chemistry, and overall ink formulation. Designers must carefully weigh feature size targets against throughput requirements. High-throughput methods like screen printing excel at volume but struggle with tight trace pitches, whereas electro-hydrodynamic (EHD) jetting and aerosol jetting achieve sub-micron line-space resolutions at the cost of processing speed.
This trade-off space directly impacts how AME is integrated into the heterogeneous integration (HI) roadmap. Heterogeneous integration is the current frontier of advanced packaging, demanding the dense integration of embedded dies, passive components, compact interconnects, and antenna shielding into a highly condensed system-in-package (SiP) form factor.
As electronics manufacturing transitions toward co-packaging and silicon-level miniaturization, understanding where AME processes can be introduced into existing assembly lines is critical. Overlaying printing capabilities onto traditional semiconductor back-end processes represents a massive market opportunity for high-yield consumer electronics.
In this short video, you can learn:
* How to navigate the trade-off matrix between printing throughput and sub-micron feature size resolution.
* The structural requirements for implementing AME into advanced heterogeneous integration (HI) packages.
* The physical limitations of screen printing versus direct-write aerosol and EHD jetting over complex 3D topologies.
š **Clip Abstract**
Kris Erickson explains how selecting the proper additive electronics manufacturing method requires balancing throughput against targeted trace resolutions. He highlights the role of AME within advanced heterogeneous integration (HI) packaging, mapping out how these digital technologies can density multi-layer substrates.
#EHDJetting, #AerosolJetPrinting, #HeterogeneousIntegration, #SubMicronResolution, #AdditiveManufacturedElectronics, #AdvancedPackaging
00:13:23 - 00:14:40
Why do micro-printed dielectric materials suffer catastrophic mechanical failure during standard package reflow?
Why do micro-printed dielectric materials suffer catastrophic mechanical failure during standard package reflow?
For additive manufactured electronics to succeed in high-volume production, printed assemblies must pass rigorous qualification tests, including thermal cycling from -55Ā°C to 125Ā°C and 85/85 accelerated aging. The primary barrier to passing these tests lies in the mismatch of the Coefficient of Thermal Expansion (CTE) between the printed inks, organic dielectrics, and silicon dies.
During high-temperature thermal cycling, mismatched CTE values induce severe localized mechanical stresses, leading to package warpage, trace delamination, and joint failure. Additionally, under high humidity, micro- and nano-pores within the printed dielectric absorb atmospheric moisture at rates orders of magnitude higher than bulk materials.
When the device undergoes solder reflow, this trapped moisture vaporizes instantly, causing "popcorning" and structural rupture of the printed layers. Mitigating these failures requires a meticulous co-design of ink chemistries, curing kinetics, and advanced hermetic encapsulation layers to survive real-world environments.
In this short video, you can learn:
* How CTE mismatches between printed conductors and dielectrics lead to mechanical delamination during thermal cycling.
* The physical mechanism behind moisture absorption in nanoporous printed dielectrics and subsequent reflow "popcorning."
* Why standard environmental testing (85Ā°C/85% RH) poses a critical barrier to qualifying additive electronics.
š **Clip Abstract**
Kris Erickson highlights the critical reliability challenges of printed electronics under environmental testing. He discusses how thermal CTE mismatches and moisture vapor expansion in printed nanopores cause catastrophic package failure during reflow.
#ReflowPopcorning, #NanoporousDielectrics, #CteMismatch, #ThermalCycling, #AdditiveManufacturedElectronics, #SemiconductorPackaging