Michael Gleason | Greensource Fabrication: How does thermal expansion mismatch between the dielectric material and vias lead to potential failures, and what testing methodologies are employed to mitigate these risks?
00:06:17 - 00:06:27
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How does thermal expansion mismatch between the dielectric material and vias lead to potential failures, and what testing methodologies are employed to mitigate these risks?
The speaker addresses the critical issue of reliability, particularly concerning the thermal expansion mismatch between the dielectric material and the vias in a PCB. This mismatch can lead to stress and strain on the via interconnections during thermal cycling, potentially causing them to pull apart and resulting in latent failures in the field. The speaker emphasizes the importance of robust via structures to withstand these stresses.
To mitigate these risks, the company employs rigorous testing methodologies, including subjecting the PCBs to multiple reflow cycles at elevated temperatures (230Ā°C, 245Ā°C, and 260Ā°C). These reflow cycles simulate the thermal stresses experienced during the assembly process and in-field operation. The PCBs are then tested for changes in resistance, which indicate the integrity of the via interconnections.
By performing these tests, the company can identify potential weaknesses in the via structures and ensure that they are robust enough to withstand the thermal stresses encountered in real-world applications. This proactive approach helps to prevent latent failures and improve the overall reliability of the PCBs.
In this short video, you can learn:
* The potential reliability issues caused by thermal expansion mismatch in PCBs.
* The testing methodologies used to simulate thermal stresses and identify weaknesses.
* The importance of robust via structures in preventing latent failures.
š **Clip Abstract** The speaker explains how thermal expansion differences between dielectric materials and vias can cause failures, and details the rigorous testing process involving multiple reflow cycles at high temperatures to identify and prevent these potential issues, ensuring PCB reliability. This testing simulates assembly and operational thermal stresses.
š Link in comments š
#ThermalExpansionMismatch, #ViaReliability, #PCBStressTesting, #DielectricVias, #SemiconductorPackaging, #ElectronicsReliability
This is a highlight of the presentation:
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00:02:07 - 00:02:15
How does building copper directly on a dielectric material enhance circuit density compared to using a copper foil seed layer?
How does building copper directly on a dielectric material enhance circuit density compared to using a copper foil seed layer?
The speaker highlights a key aspect of their expansion: pure SAP (Semi-Additive Process) manufacturing. This involves building copper directly onto a dielectric material, contrasting with the more traditional mSAP (modified Semi-Additive Process) which utilizes a copper foil seed layer. The transition to pure SAP is driven by the pursuit of greater circuit density, particularly for applications like IC packaging.
The distinction between pure SAP and mSAP lies in the initial copper layer. mSAP starts with a thin copper foil, which is then patterned and plated. Pure SAP, however, begins with a bare dielectric, onto which copper is selectively deposited. This eliminates the need for etching away large areas of copper foil, allowing for finer lines and spaces.
The ability to directly build copper on the dielectric offers several advantages. It enables the creation of finer features, reduces material waste, and improves signal integrity. This is crucial for advanced applications requiring high density interconnects and superior electrical performance.
In this short video, you can learn:
* The difference between pure SAP and mSAP PCB manufacturing.
* How pure SAP enables higher density circuits.
* The advantages of building copper directly on a dielectric.
š **Clip Abstract** The speaker explains the company's move towards pure SAP manufacturing, emphasizing its advantage in achieving higher circuit density compared to traditional mSAP processes that use a copper foil seed layer. This transition is crucial for applications like IC packaging where miniaturization and performance are paramount.
š Link in comments š
#PureSAP, #mSAP, #DirectCopperOnDielectric, #CircuitDensity, #ICPackaging, #HighDensityInterconnects
00:04:53 - 00:05:00
What are the key process steps and advantages of achieving a 10:1 aspect ratio plated shut mechanical via, and why is it considered unique, especially in the US?
What are the key process steps and advantages of achieving a 10:1 aspect ratio plated shut mechanical via, and why is it considered unique, especially in the US?
The speaker emphasizes their capability to produce high aspect ratio vias, specifically mentioning a 10:1 aspect ratio plated shut mechanical via. This is presented as a unique achievement, particularly within the United States. The high aspect ratio signifies a deep, narrow via, which poses significant challenges in terms of plating uniformity and reliability.
The process involves mechanically drilling the via, followed by a plating process to deposit copper on the via walls. Achieving a 10:1 aspect ratio requires precise control over the plating chemistry, current density, and agitation to ensure uniform copper deposition throughout the depth of the via. The "plated shut" aspect indicates that the via is completely filled with copper, eliminating voids and enhancing its structural integrity and electrical conductivity.
The uniqueness of this capability, especially in the US, suggests that it requires specialized equipment, expertise, and process control that are not widely available. The ability to reliably produce such high aspect ratio vias is a significant differentiator, enabling the creation of more complex and compact circuit board designs.
In this short video, you can learn:
* What a high aspect ratio via is and why it's challenging to manufacture.
* The process steps involved in creating a plated shut mechanical via.
* Why achieving a 10:1 aspect ratio via is considered unique, especially in the US.
š **Clip Abstract** The speaker highlights their ability to manufacture 10:1 aspect ratio plated shut mechanical vias, emphasizing the difficulty and uniqueness of this process, particularly within the United States, suggesting specialized expertise and equipment are required. This capability enables more complex and compact circuit board designs.
š Link in comments š
#HighAspectRatioVia, #PlatedShutVia, #ViaElectroplating, #MechanicalViaDrilling, #AdvancedPackaging, #PCBFabrication