* Members only
Semiconductor Package Design Solution for High Density Fan-out Packaging – Chiplets & SiP
There is great need for multi-die packaging – Chipletes & SiP – to meet the needs of High Performance Computing for Data Ceteers, 5G, Accelerators, AI & ML, & Autonomous Driving applicatiopns and more. A good example of the package type used in such high-performance computing product mass production is Silicon Interposer IC package with ultra-high density I/O, for high performance GPU, and high-speed networking devices, Between the ASIC chip and the HBM stack, a lot of high-speed signal lines and thousands of small vias are connected. In addition the silicon interposer has an important structure-TSV (Through Silicon Via) to act as the connection between the ASIC chips or the HBM chips and the package substrate. Considering productivity and cost, there is great need to develop an advanced packaging solution to fill in the “Gap” between Flip Chip BGA based high density build up substrate and silicon Inteerposer with TSV. One such solution would be high density Fan-Out based upon the well known and well established robust Wafter Level Fanout process and manufacturing infrastructure.
In this paper, we report on an internally developed semiconductor package design flow and platform is proposed for FOCoS package. The platform integrates with semiconductor package design solution and integrated circuit (IC) design solution. It can balance the developing schedule and cost in the design stage of FOCoS. The design flow of FOCoS includes physical design, design rule check (DRC), layout versus schematic (LVS) check and full wave electromagnetic (EM) analysis. In physical design, the major design platform is still based on conventional package design solution like Cadence Allegro APD+ or Mentor XPD. But, to speed up design cycle time, the auto-router for FOCoS RDL design is used in IC design solution. A self-developing program linking to conventional package design solution and IC design solution is applied on the two different file format transferred. Therefore, the FOCoS RDL designer can utility the auto-router to complete the preliminary design, then transfer the design file to conventional package design platform for modification. Once the design is completed, the DRC and LVS can confirm the correctness in rules and interconnection. The difference with IC design flow, it utilizes package netlist to do LVS check in this platform, not schematics. Hence, it easily uses the program of LVS to do 3D IC check. In addition, the location of DRC error can be imported to conventional package design platform and the designer can fast fix the error in conventional package design platform. Finally, the full wave 3D solver extracts the S-parameter of die-to-die or die-to-HBM interconnection for electrical analysis. A real case using the design flow is demonstrated with design cycle time reduction. This design flow is integrated in the package & assembly PDK for HD Fanout package. We shall incorporate AI & ML tools to futher optimize the design process in the future.
Bio: Chen-Chao Wang received the M.S.E.E. degree in electronic engineering from the National Taiwan University of Science and Technology, Taipei, in 1998 and Ph.D. degree in electrical engineering from the National Sun Yat-sen University, Kaohsiung, in 2008, respectively. From 1998 to 2003, he was a Research Engineer at Industrial Technology Research Institute, Hsinchu, Taiwan. In 2006, he joined Advanced Semiconductor Engineering Inc., Kaohsiung, Taiwan, where he is in charge of Division of Product Design. His researching direction includes power integrity and signal integrity analysis in high-speed digital systems and mmWave antenna-in-package design.
ASE Fellow & Senior Technical Advisor, Life Fellow of IEEE
The HIR Village for the Heterogeneous Future
Bio: Dr William Chen (Bill) holds the position of ASE Fellow & Senior Technical Advisor at ASE Group. Prior to joining the ASE, he was Director at the Institute of Materials Research & Engineering (IMRE) in Singapore, following a distinguished career at IBM Corporation. Bill is a past President of the IEEE Electronics Packaging Society. He is a Life Fellow of IEEE and a Fellow of ASME. He received the ASME InterPACK Achievement Award in 2007. In 2018, he received the IEEE Electronics Packaging Field Award, recognizing his contribution to electronic packaging, from research & development through industrialization.
Bill chairs the Heterogeneous Integration Roadmap initiative, co-sponsored by 3 IEEE Societies (EPS, EDS & Photonics) together with SEMI & ASME Electronics & Photonics Packaging Division.
Director of Alabama Micro/Nano Science and Technology Center
Superconducting Interconnect Technologies for Cryogenic and Quantum Systems
Superconducting electronics and quantum systems are experiencing a significant growth in interest due to recent successes in superconducting quantum computing. Cryogenic electronics systems present a unique set of challenges for complex, densely integrated systems with large numbers of components and cables/interconnects often spanning multiple temperature stages. Conventional microwave co-axial cables that are currently in common use can stress volume and thermal constraints of these systems. Suitable connectors for such systems are also needed. In this presentation, I will describe our R&D efforts on high performance, multi-conductor superconducting flexible cables and connectors made using thin-film and wafer-level fabrication approaches. These interconnects have high microwave performance to multiple 10’s of GHz, low mass, and low thermal cross-section structures. This hardware shows great promise as interconnect structures for future superconducting and cryogenic electronics systems, including superconducting microwave quantum computing applications.
Bio: Dr. Michael C. Hamilton obtained a BS in Electrical Engineering from Auburn University in 2000 and MS and PhD in Electrical Engineering from The University of Michigan in 2003 and 2005, respectively. From 2006 to 2010, he was at MIT-Lincoln Laboratory (Lexington, MA), where he worked on a range of microwave and solid-state device projects. Dr. Hamilton joined the Electrical and Computer Engineering Department of Auburn University in 2010 and is now James B. Davis Professor and Director of the Alabama Micro/Nano Science and Technology Center (AMNSTC). He is the Auburn University IEEE Student Chapter Faculty Advisor. Dr. Hamilton is involved with IEEE MTT-S: Education Committee, Chair of MTT-7 Technical Committee on Microwave Superconductivity and Quantum Technologies, producer/moderator of the IEEE MTT-S Webinar Series. He is currently serving on the editorial board of a new open access journal: IEEE Journal of Microwaves. His current interests and areas of research include superconductive electronics and technologies for quantum systems, micro/nano fabrication, packaging and integration of high-speed systems, signal and power integrity of densely integrated systems, application of micro and nanostructures for enhanced performance of RF and microwave systems and packaging for extreme environments (both high and low temperature).
Papertronics for Internet of Disposable Things
Disposable wireless sensor networks (WSNs) will allow every corner of the world to be connected through the Internet of Disposable Things (IoDT). This novel technique, constructed in a small, compact, disposable package at a low price point, can connect functional things inexpensively for only a programmed period and then be readily thrown away. The IoDT devices will provide a great degree of intelligence and autonomy by enabling rapid deployment of new types of IoT applications and the creation of new services at an affordable price point. Despite excitement about this conceptual paradigm for WSNs, the IoDT has not been widely explored because of requirements for substantial technological advances in independent and self-sustainable function, and the multidisciplinary nature of application-dependent WSNs. In particular, low-cost and eco-friendly IoDT devices are critical to providing disposable and biodegradable functionality as the devices are expected to be increasingly pervasive and fast updated for their rapid deployment. Paper has recently emerged as a flexible and low-cost game-changing substrate for next-generation electronics, known as papertronics, because of its excellent mechanical and dielectric properties with chemical and thermal stability. The biodegradability of papertronics has attracted much attention as the future of green electronics, reducing the dramatic increase in electronic waste. Integrated papertronics will have the transformative potential to yield exceptionally powerful functions and performances for many IoDT applications such as monitoring public health and surveilling environmental conditions. In this talk, he will present many innovative papertronic devices that his research group recently developed including paper-based PCBs, paper-based microfluidics, and paper-based batteries. Details of the frontier of research to improve the performance of the papertronics will be discussed, followed by a critical perspective on strategic future directions.
Bio: Seokheun “Sean” Choi is a Professor in the Department of Electrical & Computer Engineering at State University of New York (SUNY)-Binghamton. Currently, he is running “Bioelectronics & Microsystems Lab” and “Center for Research in Advanced Sensing Technologies & Environmental Sustainability” as a Director at SUNY-Binghamton. Prior to joining SUNY-Binghamton, he was a research professor in the School of Electronic & Computing Systems at the University of Cincinnati. He received his Ph.D. degree in bioelectronics from Arizona State University in 2011. His current research focuses on “Bioelectronics and Bioenergy technologies,” including self-powered biosensors, wearable and stretchable sensors, biobatteries, papertronics, and fibertronics. He has been recognized as a pioneer in biobatteries and paper-based bioelectronic systems. His research has been supported by government agencies and industry including NSF, ONR, IEEC, and SUNY RF. He has authored over 150 journal and conference articles, two book chapters, and one book, and hold two U.S. patents.
Examination of Electromigration Effects in Sn-Bi Based Solder Joints
A study of the effect of the variation of processing parameters on the microstructure of Pb free solder joints, and their performance under current stressing. The effect of varying reflow temperature, under bump metallurgy and solder joint geometry on the microstructure of assemblies was examined. Effects were examined of different current densities and temperatures on Bi migration in Sn-Bi based solder joints. A model of Bi accumulation in these structures was constructed and used to predicted mean times to failure.
Bio: Eric Cotts is a professor in the Materials Science program, and in the Physics department, at Binghamton University. He received his BS degree from Cornell University in 1978 and his PhD degree from the University of Illinois at Urbana-Champaign in 1983. His research group studies phase transformations in metal systems, with a focus on applications for microelectronic devices. Studies of the dependence of nucleation rates of undercooled Sn on impurity content provide insight in to control of microstructure and recommendations for the processing of interconnects. Examination of the effects of thermal history and current stressing on the microstructure of SnBi-based solders lead to expressions for the mean time to failure as a function of current density, temperature, metallization and solder joint geometry.
Defense Advanced Research Projects Agency (DARPA)
Special Assistant to the Director
Electronic Resurgence Initiative Briefing
The DARPA Microsystems Technology Office (MTO) Electronics Resurgence Initiative (ERI), initially announced in 2017, is a response to several technical and economic trends in the microelectronics sector. Among these trends, the rapid increase in the cost and complexity of advanced microelectronics design and manufacture is challenging a half-century of progress under Moore's Law, prompting a need for alternative approaches to traditional transistor scaling. Meanwhile, non-market foreign forces are working to shift the electronics innovation engine overseas and cost-driven foundry consolidation has limited Department of Defense (DoD) access to leading-edge electronics, challenging U.S. economic and security advantages. Moreover, highly publicized challenges to the nation's digital backbone are fostering a new appreciation for electronics security-a longtime defense concern.
ERI ensures far-reaching improvements in electronics performance well beyond the limits of traditional scaling. The programs make a significant investment to create a more specialized, secure, and automated electronics industry that serves the needs of both defense as well as the domestic commercial sectors. Building on the tradition of other successful government-industry partnerships, ERI aims to forge forward-looking collaborations among the commercial electronics community, defense industrial base, university researchers, and the DoD to address these challenges. Given today's cost, complexity, and security challenges, the nation now stands ready to collaboratively innovate the next wave of electronics progress.
Leveraging 3D heterogeneous integration, the next wave should support continuing electronics progress despite challenges to traditional silicon scaling. This integration will enable innovators to both add new materials and devices to the silicon foundation and create specialized functions precisely designed to meet the diverse needs of the commercial and defense sectors. To manage the complexity of working in three dimensions, the next wave will also demand new architectures and design tools that address rising design costs, enable rapid system upgrades, and make security integration a primary design concern.
Bio: Dr. Carl E. McCants is a special assistant to the DARPA director, focusing on the Microsystems Technology Office's (MTO) Electronics Resurgence Initiative (ERI) and the National Network for Microelectronics Research and Development.
Prior to his role at DARPA, he was the technical director of the Supply Chain and Cyber Directorate of the National Counterintelligence and Security Center (NCSC), in the Office of the Director of National Intelligence. McCants provided scientific and technical input and briefed senior government leaders on national-level supply chain integrity issues. He also provided subject matter expertise on microelectronics-related supply chain concerns.
From 2012 to 2018, McCants was a senior program manager at the Intelligence Advanced Research Projects Activity (IARPA), managing the Rapid Analysis of Various Emerging Nanoelectronics (RAVEN) program, the Trusted Integrated Chips (TIC) program, and the Circuit Analysis Tools (CAT) program. His IARPA programs earned him the Intelligence Community's Science & Technology Individual Contributor Award for FY2016.
From 2010 to 2012, he was a program manager in MTO at DARPA, focused on microelectronic integration and hardware assurance and reliability. From 2003 to 2009, he was an associate at Booz Allen Hamilton, where he served as the chief technologist to the director of MTO, and special assistant to the DARPA deputy director.
From 1999 to 2003, McCants was a project manager at Agilent Technologies' Semiconductor Products Group where he was responsible for front-end and back-end optical and electrical characterization of photonic devices, and automated test platform development. From 1988 to 1999, he was a development engineer at Hewlett-Packard's Optical Communication Division, where he focused on materials characterization, wafer fabrication, and photonic measurements of LEDs and lasers.
McCants received his bachelor's degree from Duke University in 1981 and his master's and doctoral degrees from Stanford University in 1982 and 1989, respectively, all in electrical engineering. He is a senior member of the IEEE.
Economic and Environmental Perspectives on Panel Level Packaging
Bio: Dr. Mathilde Billaud is a research fellow at Fraunhofer IZM since 2017. Between 2013 and 2016, she conceived a process flow in the 300mm-Silicon clean room of CEA-Leti (Grenoble, France) integrating III-V materials in CMOS transistors. She is now involved in an industrial consortium organized by Fraunhofer IZM, on Fan-Out Panel Level Packaging to model the complete process flows related to the different technology options for chip packaging on panel size developed at IZM. The modeling enables a combined cost and environmental assessment. This methodology is now transferred to other research and industrial projects. She is also part of the consortium that evaluates the requests for exemption to the restriction of hazardous substances (RoHS) directive and for the end of life vehicles directive (ELV directive) with a focus on lead-acid batteries. Her favorite research topics cover critical materials, resource and energy consumption, as well as circular practices in microelectronic manufacturing. She holds a Master’s degree from the National Graduate School of Chemistry of Montpellier (France) with an expertise in chemistry and chemical engineering. She received a doctor’s degree in 2017 for her thesis “Integration of III-V materials as high mobility channel for MOSFET transistor”.
Technologies and Applications for Wearable e-Textiles
Smart textiles have been a research topic for more than 20 years. A broad range of technologies has been developed and investigated. The solutions range from conductive or otherwise functionalized yarns to integration technologies for conventional and hybrid electronics including sensors. The maturity and scalability of these technologies have been major challenge on the way to bring the research results into the market, considering that two very different industries have to join efforts for success. Better understanding of the different technological approaches and their limitations together with the development of corresponding equipment can enable the transfer to industry. Regarding the applications, research still focuses on medical applications in the areas of prophylaxis, diagnosis, monitoring, treatment and rehabilitation. These devices are typically very specialized and optimized for different locations on the body. This specialization of the devices leads to new requirements regarding the materials, integration technologies and reliability. At the same time, it is necessary to develop and verify systems in short cycles. With modular electronic systems and textile bus structures these requirements can be met.
Bio: Christine Kallmayer received a diploma in experimental physics at the University of Kaiserslautern in 1994. Afterwards she worked as a research scientist at the research center "Technologien der Mikroperipherik“ at the Technical University of Berlin. Her main field of activity was the development and investigation of interconnection technologies with the Au-Sn metallurgy for different applications, e.g. optoelectronics and the reliability of the metallurgical system. Since 1998 she is responsible for the group „System on Flex“ at Fraunhofer IZM. The main working areas are new technologies for flip chip integration on and in flex by soldering or adhesive bonding. Especially technologies for ultrathin chips are developed and investigated. The group is also developing new flexible substrate materials, e.g. based on thermoplastic polymers, together with optimized assembly technologies. A current research focus is on stretchable and conformable electronics based on textiles as well as elastomers.