Soeren Steudel | Enkris Semiconductor Europe: How does processing displays on 4-inch wafers instead of 300mm wafers impact final manufacturing cost and yield?
19:40 - 21:23
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Summary of the clip:
How does processing displays on 4-inch wafers instead of 300mm wafers impact final manufacturing cost and yield?
At 200 mm the situation improves, but remains challenging. Wafer-to-wafer bonding and integration immediately hit cost. One example uses four-inch wafers for gallium nitride and AlInGaP with CMOS integration: a 300 mm CMOS wafer is cut out, then a four-inch process runs through the line. That approach directly determines how the manufacturing flow and final yield are impacted.
A cost calculation compares large displays, 1,500 by 1,500 and 2,560 by 2,560, with epi on 100 mm, 150 mm, 200 mm and 300 mm. Reconstitution creates an artificial 300 mm wafer. When a four-inch wafer is cut out and processed on a four-inch line, it is massively more expensive than bonding 300 mm on a 300 mm wafer. The losses are immediately a factor of two to five.
The calculation is generous to four-inch and six-inch tools because it assumes every tool generation gets the same yield, which is not the case. That automatically shows why there is a drive to make the whole process integration on a minimum 200 mm line, but better a 300 mm line. The cost difference already starts from the beginning and is a factor.
In this short video, you can learn:
* Processing four-inch GaN and AlInGaP wafers after cutting CMOS from a 300 mm wafer is massively more expensive than 300 mm-to-300 mm bonding.
* Reconstitution to an artificial 300 mm wafer shows cost structures for 100 mm, 150 mm, 200 mm and 300 mm epi across 1,500 by 1,500 and 2,560 by 2,560 displays.
* The calculation is generous to four-inch and six-inch tools by assuming equal yield across tool generations, which is not the case, driving integration to at least 200 mm or better 300 mm.
📋 **Clip Abstract** The clip compares large-display cost when epi and processing use 100 mm, 150 mm, 200 mm or 300 mm wafers, including reconstitution to an artificial 300 mm wafer. Cutting a four-inch wafer from 300 mm CMOS and running it on a four-inch line creates immediate factor-of-two-to-five losses, while assuming equal yield across tool generations is generous, explaining the push to 200 mm or 300 mm integration.
About the speaker:
* Speaker: Soeren Steudel
* Company: Enkris Semiconductor Europe
* Event: Eindhoven 2026
* Location: High Tech Campus, Eindhoven
#GalliumNitride, #AlInGaP, #WaferToWaferBonding, #300mmReconstitution, #MicroLEDManufacturing, #AdvancedDisplayPackaging
This is a highlight of the presentation:
Yield and manufacturing challenges for microLED micro-displays
More Highlights from the same talk.
06:36 - 08:35
Why is a 5-micron micro-bumping demo in R&D misleading for high-volume microLED manufacturing?
Why is a 5-micron micro-bumping demo in R&D misleading for high-volume microLED manufacturing?
A five-micrometer integration path can be made to work, but the distinction is production versus R&D: the blue is production, the yellow is R&D. A five-micrometer micro-bumping demo does not prove high-volume manufacturability. Micro bumping is established and runs in high volume for high-bandwidth memory, yet that volume is at a ten-micrometer pitch; if HBM generations five and six move to die-to-wafer hybrid bonding, new entrants will struggle.
Alternative routes exist: micro bumping with lift-off and indium bumping are used for infrared imagers and quantum computing, where smaller pitches are possible. Researchers have shown a 1.5-micrometer-pitch microLED on CMOS using indium micro bumping. That does not mean it can be produced. A perfect display may be demonstrated, but in high-volume production the yield will not be good. So the demo metrics must be separated from volume yield.
The best theoretical option is wafer-to-wafer hybrid bonding. In volume production, wafer-to-wafer hybrid bonding reaches 1.5-micrometer pitch for backside-illuminated imagers, and R&D has gone down to 200 nanometers, so there is space to go lower. The follow-up is die-to-wafer hybrid bonding, described as a super hot topic, currently on Asiram on Logic—AMD—reaching six micrometers in production; last year the question's answer was seven micrometers.
In this short video, you can learn:
* A five-micrometer micro-bumping demo in R&D does not establish high-volume microLED manufacturing yield.
* High-volume micro bumping is driven by high-bandwidth memory at a ten-micrometer pitch.
* Wafer-to-wafer hybrid bonding reaches 1.5-micrometer pitch in production, while die-to-wafer hybrid bonding is at six micrometers for AMD.
📋 **Clip Abstract** The clip distinguishes R&D demonstrations from production realities for microLED micro-displays, using micro bumping and hybrid bonding as examples. It shows that volume, pitch, and yield, not a five-micrometer demo alone, determine whether a manufacturing path can scale.
About the speaker:
* Speaker: Soeren Steudel
* Company: Enkris Semiconductor Europe
* Event: Eindhoven 2026
* Location: High Tech Campus, Eindhoven
#MicroBumping, #IndiumBumping, #WaferToWaferHybridBonding, #DieToWaferHybridBonding, #AdvancedPackaging, #MicroLEDDisplays
25:04 - 27:20
Dedicated microLED fab or standard foundry: which CapEx path wins when volumes slip a decade?
Dedicated microLED fab or standard foundry: which CapEx path wins when volumes slip a decade?
Building a dedicated 100 mm to 300 mm fab costs $100M–$500M for the most basic, non-throughput-optimized module. You buy the ASIC from a standard foundry but run both the integration flow and the LED flow in-house, at super-high CapEx. Because microLED volume ramp-up has been delayed eight years, that CapEx burns every year while the fab waits for production load.
A large Silicon Valley backer once asked for 20 million units in 2022; the answer was that this was too fast. The target year is now 2026, and the speaker does not expect 20 million units before 2030. A dedicated fab therefore simply burns CapEx, even though it brings medium R&D cost, a fast learning cycle, and die cost only if you can provide a full fab load.
The preferred route runs in an existing standard foundry: make the process fit so the same line runs the ASIC and the LED process. A complete flow was developed and verified by multiple foundries, including GlobalFoundries, which agreed but demands significant volume commitments. The trade-off is very low CapEx against very high R&D cost, because the flow cannot be developed inside the foundry itself, yet it delivers optimal production cost.
In this short video, you can learn:
* A basic dedicated 100 mm to 300 mm microLED fab module costs $100M–$500M before any throughput optimization.
* Foundries such as GlobalFoundries will accept the LED process flow only in exchange for significant volume commitments.
* The standard-foundry route gives very low CapEx and optimal production cost, but pushes R&D cost very high because the flow cannot be developed there.
📋 **Clip Abstract** Dedicated microLED fabs carry $100M–$500M CapEx on a basic module and burn it yearly while volumes slip, with 20 million units now unlikely before 2030. Running the LED integration flow inside an established foundry such as GlobalFoundries cuts CapEx and optimizes production cost, but requires major volume commitments and far higher R&D spend.
About the speaker:
* Speaker: Soeren Steudel
* Company: Enkris Semiconductor Europe
* Event: Eindhoven 2026
* Location: High Tech Campus, Eindhoven
#MicroLEDFab, #FoundryVolumeCommitment, #ASICIntegration, #FabCapEx, #MicroLEDDisplays, #SemiconductorManufacturing
13:46 - 15:13
Why do microLED micro-displays need 28nm or 22nm CMOS rather than legacy nodes?
Why do microLED micro-displays need 28nm or 22nm CMOS rather than legacy nodes?
In movie studios, where chromaticity correction is done, the number of correction bits explodes. Pulse width modulation brings a flicker problem. You can reshuffle the bits on the chip itself, or massively overdrive them: at a 60 hertz frame rate, you show the same pulse width modulation sequence four times, driving at 240 or 480. Those crazy frames-per-second numbers you see on microLED displays are usually just the overdrive frequency, not the real frames shown.
That overdrive means you need a lot of SRAM, because you cannot load new data every time; the SRAM has to be on-chip. That pushes you to at least a 28 nanometer node on a 300-millimeter wafer. With that you can do the factory calibration: gamma correction and XY rotational offset correction, plus some dynamic recalibration of your display as well.
So the minimum you need is 28 nanometer on a 300-millimeter wafer, and probably rather you go to 22 or 14 nanometer. As the opening slide put it, the challenge is not realizing the best microLED, but a yielding integration flow. The advanced CMOS node is the platform that holds the on-chip SRAM, the correction bits and the recalibration.
In this short video, you can learn:
* Showing the same pulse width modulation sequence four times at 60 hertz produces the 240 and 480 frames-per-second overdrive numbers seen on microLED displays.
* On-chip SRAM is mandatory for that overdrive, which forces at least a 28 nanometer node on a 300-millimeter wafer.
* That node also enables factory calibration, gamma correction and XY rotational offset correction, plus dynamic recalibration of the display.
📋 **Clip Abstract** The clip explains why PWM flicker in microLED micro-displays is fought with bit reshuffling and overdrive, and why that demands on-chip SRAM and advanced CMOS nodes. It lands on 28 nanometer on 300 millimeters as the minimum, with 22 or 14 nanometer likely, because the real challenge is a yielding integration flow rather than the best microLED.
About the speaker:
* Speaker: Soeren Steudel
* Company: Enkris Semiconductor Europe
* Event: Eindhoven 2026
* Location: High Tech Campus, Eindhoven
#MicroLEDMicroDisplay, #PulseWidthModulation, #OnChipSRAM, #GammaCorrection, #MicroLEDDisplays, #ARVRDisplays