Advanced Packaging Architectures: Opportunities and Challenges

Advanced packaging architectures are today widely acknowledged as being increasingly important to drive performance and cost improvements of microelectronics systems. As a result, several innovative packaging architectures have been announced in recent years. On-package integration provides a compact, power efficient platform for Heterogeneous Integration of diverse IP that support faster time to market and cost/yield benefits. In this talk, I will describe current technology envelopes and future scaling directions for representative advanced packaging architectures. Key areas of focus will be: (1) Interconnect scaling, (2) Power efficient high bandwidth signaling including optical interconnects, (3) Hybrid Bonding, (4) Test challenges for chiplets/die block assembly, and (5) Advanced power delivery technologies. The talk will conclude with a call for broad collaboration across industry and academia in multiple areas including technology R&D, design, standardization, and supply chain development.

Bio: Babak Sabi is a Corporate Vice President and the General Manager of Assembly & Test Technology Development (ATTD) at Intel Corporation. Since 2009, he has been responsible for the company’s packaging, assembly process and test technology development.

Babak joined Intel in 1984. Prior to leading ATTD, he led the Corporate Quality Network within Intel’s Technology & Manufacturing Group from 2002 to 2009. He managed a company-wide network of quality and reliability organizations responsible for product reliability, customer satisfaction and quality business practices.

Babak received his Ph.D. in solid state electronics from Ohio State University in 1984. He has authored ten papers on reliability physics and has received five Intel Achievement Awards. He currently holds two patents.