Semiconductor Package Design Solution for High Density Fan-out Packaging – Chiplets & SiP

There is great need for multi-die packaging – Chipletes & SiP – to meet the needs of High Performance Computing for Data Ceteers, 5G, Accelerators, AI & ML, & Autonomous Driving applicatiopns and more. A good example of the package type used in such high-performance computing product mass production is Silicon Interposer IC package with ultra-high density I/O, for high performance GPU, and high-speed networking devices, Between the ASIC chip and the HBM stack, a lot of high-speed signal lines and thousands of small vias are connected. In addition the silicon interposer has an important structure-TSV (Through Silicon Via) to act as the connection between the ASIC chips or the HBM chips and the package substrate. Considering productivity and cost, there is great need to develop an advanced packaging solution to fill in the “Gap” between Flip Chip BGA based high density build up substrate and silicon Inteerposer with TSV. One such solution would be high density Fan-Out based upon the well known and well established robust Wafter Level Fanout process and manufacturing infrastructure.

In this paper, we report on an internally developed semiconductor package design flow and platform is proposed for FOCoS package. The platform integrates with semiconductor package design solution and integrated circuit (IC) design solution. It can balance the developing schedule and cost in the design stage of FOCoS. The design flow of FOCoS includes physical design, design rule check (DRC), layout versus schematic (LVS) check and full wave electromagnetic (EM) analysis. In physical design, the major design platform is still based on conventional package design solution like Cadence Allegro APD+ or Mentor XPD. But, to speed up design cycle time, the auto-router for FOCoS RDL design is used in IC design solution. A self-developing program linking to conventional package design solution and IC design solution is applied on the two different file format transferred. Therefore, the FOCoS RDL designer can utility the auto-router to complete the preliminary design, then transfer the design file to conventional package design platform for modification. Once the design is completed, the DRC and LVS can confirm the correctness in rules and interconnection. The difference with IC design flow, it utilizes package netlist to do LVS check in this platform, not schematics. Hence, it easily uses the program of LVS to do 3D IC check. In addition, the location of DRC error can be imported to conventional package design platform and the designer can fast fix the error in conventional package design platform. Finally, the full wave 3D solver extracts the S-parameter of die-to-die or die-to-HBM interconnection for electrical analysis. A real case using the design flow is demonstrated with design cycle time reduction. This design flow is integrated in the package & assembly PDK for HD Fanout package. We shall incorporate AI & ML tools to futher optimize the design process in the future.

Bio: Chen-Chao Wang received the M.S.E.E. degree in electronic engineering from the National Taiwan University of Science and Technology, Taipei, in 1998 and Ph.D. degree in electrical engineering from the National Sun Yat-sen University, Kaohsiung, in 2008, respectively. From 1998 to 2003, he was a Research Engineer at Industrial Technology Research Institute, Hsinchu, Taiwan. In 2006, he joined Advanced Semiconductor Engineering Inc., Kaohsiung, Taiwan, where he is in charge of Division of Product Design. His researching direction includes power integrity and signal integrity analysis in high-speed digital systems and mmWave antenna-in-package design.